Avoid unnecessary AArch64 DSB in __clear_cache in some situations.

The dsb after instruction cache invalidation only needs to be executed
if any instruction cache invalidation did happen.
Without this change, if the CTR_EL0.DIC bit indicates that instruction
cache invalidation is not needed, __clear_cache would execute two dsb
instructions in a row; with the second one being unnecessary.

Differential Revision: https://reviews.llvm.org/D104371