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Commit 70f50114 authored by Craig Topper's avatar Craig Topper
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[RISCV] Add another isel optimization for (and (shl x, c2), c1)

Turn (and (shl x, c2), c1) -> (slli (srli x, c3-c2), c3) if c1 is a
shifted mask with no leading zeros and c3 trailing zeros where c3
is greater than c2.
parent 8811227a
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