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Commit 715cf6ff authored by Craig Topper's avatar Craig Topper
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[RISCV] Add another isel optimization for (and (shl X, c2), c1).

Where c1 is a shifted mask with 32-c2 leading zeros and c3 trailing
zeros and c3>c2. We can select it as (slli (srliw X, c3-c2), c3).
parent d0649320
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