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Commit 7b365028 authored by Michael Maitland's avatar Michael Maitland
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[RISCV][CodeGen] Account for LMUL for Vector Integer load store instructions 

It is likley that subtargets act differently for a vector load store instructions based on the LMUL.
This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL.

Differential Revision: https://reviews.llvm.org/D137429
parent 1a43227b
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