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Commit 7ba830d6 authored by Sanjoy Das's avatar Sanjoy Das
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Fix machine instruction in test case

The AMD64rm instruction used in the test case was incorrect.  Since
the first input register to AND64rm is tied to output register, they
must be the same.

Thanks for Jesper Antonsson for pointing this out!

llvm-svn: 305756
parent de6cce22
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