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Commit 8c0b88c9 authored by Bradley Smith's avatar Bradley Smith
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[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also... 

[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.

llvm-svn: 205865
parent 527bf86e
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