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Commit 9202c9fb authored by Simon Pilgrim's avatar Simon Pilgrim
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[X86] ROR*mCL instruction models should match ROL*mCL etc. 

Confirmed with Craig Topper - fix a typo that was missing a Port4 uop for ROR*mCL instructions on some Intel models.

Yet another step on the scheduler model cleanup marathon......

llvm-svn: 342846
parent b3478fcf
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