[AMDGPU] Define DWARF encoding for condition code registers

Summary:
- Define DWARF register numbers for vector and scalar condition codes.
- Document intended purpose of reserved DWARF register numbers.

Reviewers: yaxunl, kzhuravl, arsenm, rampitec, b-sumner

Subscribers: jvesely, wdng, nhaehnle, aprantl, dstuttard, tpr, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82519