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Unverified Commit ab89cfd0 authored by Yeting Kuo's avatar Yeting Kuo Committed by GitHub
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[RISCV] Use vwsll.vi/vx + vwaddu.wv to lower vector.interleave when Zvbb enabled. (#67521)

The replacement could avoid an assignment to GPR when the type is vector
of i8/i16 and vwmaccu.wv which may have higher cost than vwsll.vi/vx.
parent 0f339e65
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