[AArch64][SME] SelectSMETileSlice should also match to 'reg+0' when slice is...

[AArch64][SME] SelectSMETileSlice should also match to 'reg+0' when slice is ADD with non-constant RHS.

It would decompose an address into a `reg + 0` when the slice was not an ADD,
but when the RHS of the ADD was not a constant, it would simply not match.

This patch fixes that, by always resolving to a `reg + 0` slice.