[InstCombine] [InstCombine] reduce left-shift-of-right-shifted constant via demanded bits

If we don't demand low bits and it is valid to pre-shift a constant:
(C2 >> X) << C1 --> (C2 << C1) >> X

https://alive2.llvm.org/ce/z/_UzTMP

This is the reverse-order shift sibling to 82040d41 ( D127122 ).
It seems likely that we would want to add this to the SDAG version of
the code too to keep it on par with IR.