[RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

Based on the following description from Andrew W.

- Instructions not mentioned here behave the same as integer ALU ops
- rev8 only executes in the late-A and late-B ALUs
- shNadd[.uw] only execute on the early-B and late-B ALUs
- clz[w], ctz[w], and orc.b and all rotates only execute in the late-B ALU
- pcnt[w] looks exactly like integer multiply

This patch does not account for early/late ALU in the model. It is coded based
on the pipes only.

Differential Revision: https://reviews.llvm.org/D149497



Co-Authored-By: topperc <craig.topper@sifive.com>