[RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing...

[RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter.

This adds a special operand type that is allowed to be either
an immediate or register. By giving it a unique operand type the
machine verifier will ignore it.

This perturbs a lot of tests but mostly it is just slightly different
instruction orders. Something bad did happen to some min/max reduction
tests. We're spilling vector registers when we weren't before.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D101246