[AArch64][GISel] Handling for G_VECREDUCE_FMIN and G_VECREDUCE_FMAX

This adds legalization for G_VECREDUCE_FMIN and G_VECREDUCE_FMAX, where the
selection can go via tablegen patterns. I haven't tried to get non-power2 types
working yet, just the more legal types.

Differential Revision: https://reviews.llvm.org/D156614