[RegisterCoalescer] fix dst subreg replacement during remat copy trick

Instructions might use definition register as its "undef" operand. It
happens on architectures with predicated executon:

```
%0:subreg = instruction op_1, ..., op_N, undef %0:subreg, op_N+2, ...
```

RegisterCoalescer should take into account all remat instruction
operands during destination subregister fixup.

```
; remat result before fix:
%1 = instruction op_1, ..., op_N, undef %1:subreg, op_N+2, ...

; remat result after fix (correct):
%1 = instruction op_1, ..., op_N, undef %1, op_N+2, ...
```

Differential Revision: https://reviews.llvm.org/D125657