[LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support

This change :

    - Fixes offsets of all register sets for Mips.
    - Adds MSA register set and FRE=1 mode support for FP register set.
    - Separates lldb register numbers and register infos of freebsd/mips64 from linux/mips64.
    - Re-orders the register numbers of all kinds for mips to be consistent with freebsd order of register numbers.
    - Eliminates ENABLE_128_BIT_SUPPORT and union ValueData from Scalar.cpp and uses llvm::APInt and llvm::APFloat for all integer and floating point types.

Reviewers : emaste, jaydeep, clayborg
Subscribers : emaste, mohit.bhakkad, nitesh.jain, bhushan
Differential : http://reviews.llvm.org/D10919

llvm-svn: 244308