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Commit e0fbd990 authored by Matt Devereau's avatar Matt Devereau
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[AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD 

Following on from https://reviews.llvm.org/D128902, lower DUPLANE128 to LD1RQD
for integer load types from instruction selection.

Differential Revision: https://reviews.llvm.org/D130010
parent 2feb99b0
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