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Commit e3283857 authored by Craig Topper's avatar Craig Topper
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Revert "[RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the... 

Revert "[RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the instruction register numbering."

This reverts commit b634f8a6.

I broke the SimplifyDemandedBits code, but we don't have tests.
parent 755dc07d
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