rev16 instruction is being generated for a half word byte swap on a 32-bit...

rev16 instruction is being generated for a half word byte swap on a 32-bit input as a bswap+rotr. This is not true for a 64-bit input.

This patch implements the rev16 instruction for a AArch64 backend for a half word byte swap on a 64-bit input.

Differential Revision: https://reviews.llvm.org/D122643