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Commit f1cc7913 authored by Simon Pilgrim's avatar Simon Pilgrim
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[X86] Add test case showing incorrect and(sextinreg(v0,i2),sextinreg(v1,i5))... 

[X86] Add test case showing incorrect and(sextinreg(v0,i2),sextinreg(v1,i5)) -> sextinreg(and(v0,v1),i2) fold
parent 2e0bf67d
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