Commits · 0232f2d36d0af5adb60c35774795e11eca0e9be2 · Roger Ferrer / llvm-epi · GitLab

Oct 10, 2020
- [X86] Check if call is indirect before emitting NT_CALL · e0b89df2
  Joao Moreira authored Oct 09, 2020
  e0b89df2
Oct 09, 2020
- [WebAssembly] Prototype i16x8.q15mulr_sat_s · d8f58bf5
  Thomas Lively authored Oct 09, 2020
  d8f58bf5
- [Hexagon] Remove ISD node VSPLATW, use VSPLAT instead · 6fd994b4
  Krzysztof Parzyszek authored Oct 08, 2020
  6fd994b4
- [Hexagon] Generalize handling of SDNodes created during ISel · 33bb3efb
  Krzysztof Parzyszek authored Oct 08, 2020
  33bb3efb
- [X86] When expanding LCMPXCHG16B_NO_RBX in EmitInstrWithCustomInserter,... · f34bb069
  Craig Topper authored Oct 09, 2020
  f34bb069
- [X86] Don't copy kill flag when expanding LCMPXCHG16B_SAVE_RBX · 662024df
  Craig Topper authored Oct 09, 2020
  662024df
- [BPF] Make BPFAbstractMemberAccessPass required · 2218e6d0
  Arthur Eubanks authored Oct 06, 2020
  2218e6d0
- [AMDGPU] Only enable mad/mac legacy f32 patterns if denormals may be flushed · 1dfbc2ea
  Jay Foad authored Oct 09, 2020
  1dfbc2ea
- [Hexagon] Return 1 instead of 0 from getMaxInterleaveFactor · 99cafe00
  Krzysztof Parzyszek authored Oct 09, 2020
  
  99cafe00
- [SystemZ] Use LA instead of AGR in eliminateFrameIndex(). · d851495f
  Jonas Paulsson authored Oct 08, 2020
  d851495f
- [DAGCombiner] Add decomposition patterns for Mul-by-Imm. · e9fd8823
  Esme-Yi authored Oct 09, 2020
  e9fd8823
- [MCRegister] Simplify isStackSlot & isPhysicalRegister and delete isPhysical. NFC · 2c4c2dc2
  Fangrui Song authored Oct 08, 2020
  
  2c4c2dc2
- [AMDGPU] Fix mai hazard VALU to LD/ST · a4f35ab2
  Austin Kerbow authored Oct 08, 2020
  a4f35ab2
- [X86] Fix some clang-tidy bugprone-argument-comment issues · e36a41b3
  Fangrui Song authored Oct 08, 2020
  
  e36a41b3
- [NFC][MC] MCRegister API typing. · 4cfc4025
  Mircea Trofin authored Oct 07, 2020
  4cfc4025
Oct 08, 2020
- [WebAssembly] Handle indirect uses of longjmp · 750b3ddd
  Heejin Ahn authored Oct 08, 2020
  750b3ddd
- [AVR] Fix null dereference warning. NFCI. · df9ae806
  Simon Pilgrim authored Oct 08, 2020
  df9ae806
- [AMDGPU] Add patterns for mad/mac legacy f32 instructions · 7238faa4
  Jay Foad authored Oct 06, 2020
  7238faa4
- [AIX] add new option -mignore-xcoff-visibility · 92bca128
  diggerlin authored Oct 08, 2020
  92bca128
- [AMDGPU] Use isLegalMUBUFImmOffset more · f53b43c0
  Sebastian Neubauer authored Oct 07, 2020
  f53b43c0
- [AMDGPU][MC][GFX1030] Disabled v_mac_f32 · 1e756688
  Dmitry Preobrazhensky authored Oct 08, 2020
  1e756688
- AArch64: treat MC expressions as 2s complement arithmetic. · 38348fa2
  Tim Northover authored Sep 22, 2020
  38348fa2
- [AMDGPU] Prefer SplitVectorLoad/Store over expandUnalignedLoad/Store · 7c88d13f
  Mirko Brkusanin authored Oct 06, 2020
  7c88d13f
- BPF: fix incorrect DAG2DAG load optimization · 31611721
  Yonghong Song authored Oct 07, 2020
  31611721
- [X86] Fix bug in -mlvi-cfi that may clobber a live register · ad4313fc
  Scott Constable authored Oct 07, 2020
  ad4313fc
- [X86] Move findDeadCallerSavedReg() into X86RegisterInfo · dc3dba7d
  Scott Constable authored Oct 07, 2020
  dc3dba7d
- [ImplicitNullChecks] Support complex addressing mode · 35cb45c5
  Anna Thomas authored Sep 24, 2020
  35cb45c5
- [X86] Defer the creation of LCMPXCHG16B_SAVE_RBX until finalize-isel · 68e1a8d2
  Craig Topper authored Oct 07, 2020
  68e1a8d2
Oct 07, 2020
- Fix MSVC "not all control paths return a value" warning. NFCI. · 03280055
  Simon Pilgrim authored Oct 07, 2020
  
  03280055
- [AMDGPU] Add tied operand to d16 scratch loads · 45014ce3
  Stanislav Mekhanoshin authored Oct 06, 2020
  45014ce3
- [AMDGPU] Use default zero flag operands in flat scratch · 7361ce73
  Stanislav Mekhanoshin authored Oct 06, 2020
  7361ce73
- [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. · 322d0afd
  Amara Emerson authored Oct 02, 2020
  322d0afd
- [WebAssembly] Rename Emscripten EH functions · 3bba91f6
  Heejin Ahn authored Sep 28, 2020
  3bba91f6
- BPF: add AdjustOpt IR pass to generate verifier friendly codes · ddf1864a
  Yonghong Song authored Aug 06, 2020
  ddf1864a
- [AMDGPU] Support disassembly for AMDGPU kernel descriptors · 528057c1
  Ronak Chauhan authored Oct 07, 2020
  528057c1
- [SVE] Lower fixed length VECREDUCE_OR operation · 333b2ab6
  Cameron McInally authored Oct 07, 2020
  333b2ab6
- [AMDGPU][MC] Improved diagnostics for instructions with missing features · 4a7e7620
  Dmitry Preobrazhensky authored Oct 07, 2020
  4a7e7620
- [AMDGPU] Implement hardware bug workaround for image instructions · f71f5f39
  Rodrigo Dominguez authored Apr 03, 2020
  f71f5f39
- BPF: avoid duplicated globals for CORE relocations · edd71db3
  Yonghong Song authored Oct 06, 2020
  edd71db3
- [PowerPC] implement target hook getTgtMemIntrinsic · f0560870
  Chen Zheng authored Sep 27, 2020
  f0560870