Commits · 059825b0f86458dfbf1e286076bea43e59756412 · Roger Ferrer / llvm-epi · GitLab

Apr 09, 2013
- Extract a function. · c910feb4
  Jakob Stoklund Olesen authored Apr 09, 2013
  c910feb4
- Compute correct frame sizes for SPARC v9 64-bit frames. · 2cfe46fd
  Jakob Stoklund Olesen authored Apr 09, 2013
  2cfe46fd
Apr 08, 2013
- X86 cost model: Model cost for uitofp and sitofp on SSE2 · f47d2d7f
  Arnold Schwaighofer authored Apr 08, 2013
  f47d2d7f
- [ms-inline asm] Add support for ImmDisp [ Symbol ] memory operands. · fce4fab1
  Chad Rosier authored Apr 08, 2013
  fce4fab1
- Generate PPC early conditional returns · b5aa7e54
  Hal Finkel authored Apr 08, 2013
  b5aa7e54
- R600: Control Flow support for pre EG gen · 5f11dd39
  Vincent Lejeune authored Apr 08, 2013
  5f11dd39
- AArch64: remove barriers from AArch64 atomic operations. · 15410e98
  Tim Northover authored Apr 08, 2013
  15410e98
- ARM: Remove unused variable. · d56a324e
  Benjamin Kramer authored Apr 08, 2013
  d56a324e
- Cleanup and improve PPC fsel generation · 81f8799f
  Hal Finkel authored Apr 07, 2013
  81f8799f
Apr 07, 2013
- Implement LowerCall_64 for the SPARC v9 64-bit ABI. · a30f4832
  Jakob Stoklund Olesen authored Apr 07, 2013
  a30f4832
- PPC rotate instructions don't have unmodeled side effcts · 7795e47b
  Hal Finkel authored Apr 07, 2013
  7795e47b
- Most PPC M[TF]CR instructions do not have side effects · b47a69ac
  Hal Finkel authored Apr 07, 2013
  b47a69ac
- PPC pre-increment load instructions do not have side effects · d71cc3a7
  Hal Finkel authored Apr 07, 2013
  d71cc3a7
- PPC pre-increment load instructions do not have side effects · 6efd45e9
  Hal Finkel authored Apr 07, 2013
  6efd45e9
- PPC MCRF instruction does not have side effects · 933e8f03
  Hal Finkel authored Apr 07, 2013
  933e8f03
- PPC FMR instruction does not have side effects · 94072b98
  Hal Finkel authored Apr 07, 2013
  94072b98
- Implement LowerReturn_64 for SPARC v9. · edaf66b0
  Jakob Stoklund Olesen authored Apr 06, 2013
  edaf66b0
Apr 06, 2013
- SPARC v9 stack pointer bias. · 03d9f7fd
  Jakob Stoklund Olesen authored Apr 06, 2013
  03d9f7fd
- Implement PPCInstrInfo::FoldImmediate · d61d4f80
  Hal Finkel authored Apr 06, 2013
  d61d4f80
- PPC ISEL is a select and never has side effects · 8fc33e5d
  Hal Finkel authored Apr 06, 2013
  8fc33e5d
- Complete formal arguments for the SPARC v9 64-bit ABI. · 1c9a95ab
  Jakob Stoklund Olesen authored Apr 06, 2013
  1c9a95ab
- R600/SI: Add support for buffer stores v2 · 754f80ff
  Tom Stellard authored Apr 05, 2013
  754f80ff
- R600/SI: Use same names for corresponding MUBUF operands and encoding fields · 6db08eb4
  Tom Stellard authored Apr 05, 2013
  6db08eb4
- R600: Add RV670 processor · 60174bb9
  Tom Stellard authored Apr 05, 2013
  60174bb9
- R600/SI: Add processor types for each SI variant · 2f21c7e5
  Tom Stellard authored Apr 05, 2013
  2f21c7e5
- R600/SI: Avoid generating S_MOVs with 64-bit immediates v2 · edbf1eb4
  Tom Stellard authored Apr 05, 2013
  edbf1eb4
- Enable early if conversion on PPC · ed6a2859
  Hal Finkel authored Apr 05, 2013
  ed6a2859
- Correct the PPC A2 misprediction penalty · 85526f2e
  Hal Finkel authored Apr 05, 2013
  85526f2e
Apr 05, 2013
- Use the target options specified on a function to reset the back-end. · eb108bad
  Bill Wendling authored Apr 05, 2013
  eb108bad
- Reverting 178851 as it broke buildbots · 91de828f
  Renato Golin authored Apr 05, 2013
  91de828f
- [ms-inline asm] Add support for numeric displacement expressions in bracketed · 4a7005e9
  Chad Rosier authored Apr 05, 2013
  4a7005e9
- Buildbot fix for r178851: mistake was in wrong TargetRegisterInfo::getRegClass usage. · 6b53a2f5
  Stepan Dyatkovskiy authored Apr 05, 2013
  6b53a2f5
- Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated... · b309b3b3
  Stepan Dyatkovskiy authored Apr 05, 2013
  b309b3b3
- Add a SchedMachineModel for the PPC G5 · 1a958cf3
  Hal Finkel authored Apr 05, 2013
  1a958cf3
- Add a SchedMachineModel for the PPC A2 · 5fde1b03
  Hal Finkel authored Apr 05, 2013
  5fde1b03
- ARM scheduler model: Add scheduler info to more instructions and resource · fb6b9f48
  Arnold Schwaighofer authored Apr 05, 2013
  fb6b9f48
- ARM scheduler model: Swift has varying latencies, uops for simple ALU ops · 5dde1f39
  Arnold Schwaighofer authored Apr 05, 2013
  5dde1f39
- X86 cost model: Differentiate cost for vector shifts of constants · 44f902ed
  Arnold Schwaighofer authored Apr 04, 2013
  44f902ed
- CostModel: Add parameter to instruction cost to further classify operand values · b9773871
  Arnold Schwaighofer authored Apr 04, 2013
  b9773871
- Rename the current PPC BCL definition to BCLalways · e5680b3c
  Hal Finkel authored Apr 04, 2013
  e5680b3c