Commits · 0d5989bb24934802a9e6fcca63848a57a91efcc8 · Roger Ferrer / llvm-epi · GitLab

Oct 05, 2020
- [X86] Remove MWAITX_SAVE_EBX pseudo instruction. Always save/restore the full... · 4b38ceb0
  Craig Topper authored Oct 04, 2020
  4b38ceb0
Oct 04, 2020
- [X86] Sync AESENC/DEC Key Locker builtins with gcc. · a02b449b
  Craig Topper authored Oct 04, 2020
  a02b449b
- [X86] Synchronize the encodekey builtins with gcc. Don't assume void* is 16 byte aligned. · 230c57b0
  Craig Topper authored Oct 04, 2020
  230c57b0
- [X86] Synchronize the loadiwkey builtin operand order with gcc version. · 28595cbb
  Craig Topper authored Oct 04, 2020
  
  28595cbb
- [PowerPC] Add builtins for xvtdiv(dp|sp) and xvtsqrt(dp|sp). · e3475f5b
  Esme-Yi authored Oct 04, 2020
  e3475f5b
- [SDAG] fold x * 0.0 at node creation time · 2ccbf3db
  Sanjay Patel authored Oct 04, 2020
  2ccbf3db
- [X86] Add memory operand to AESENC/AESDEC Key Locker instructions. · a7e45ea3
  Craig Topper authored Oct 03, 2020
  a7e45ea3
- [X86] Add X86ISD opcodes for the Key Locker AESENC*KL and AESDEC*KL instructions · adccc0bf
  Craig Topper authored Oct 03, 2020
  adccc0bf
Oct 03, 2020
- [AArch64] Prefer prologues with sp adjustments merged into stp/ldp for WinCFI,... · 7d074057
  Martin Storsjö authored Sep 23, 2020
  7d074057
- [AArch64] Allow pairing lr with other GPRs for WinCFI · 890af2f0
  Martin Storsjö authored Sep 23, 2020
  890af2f0
- [AArch64] Match the windows canonical callee saved register order · 3780a4e5
  Martin Storsjö authored Sep 23, 2020
  3780a4e5
- [ARM] Fix pointer offset when splitting stores from VMOVDRR · 7feafa02
  David Green authored Oct 03, 2020
  7feafa02
- [ARM] Test to show incorrect pointer info. NFC · 49e34e23
  David Green authored Oct 03, 2020
  
  49e34e23
- [X86] Add missing intrinsic test for aesdecwide128kl and aesdecwide256kl.... · 63fc8499
  Craig Topper authored Oct 02, 2020
  63fc8499
- [Sparc] Remove cast that truncates immediate operands to 32 bits. · 9ae95a0f
  Brad Smith authored Oct 02, 2020
  9ae95a0f
Oct 02, 2020
- [Hexagon] Move selection of HVX multiply from lowering to patterns · f528816d
  Krzysztof Parzyszek authored Oct 01, 2020
  f528816d
- Relax newly added opcode alias check to check only for a number instead of a specific opcode. · 24f406e6
  Douglas Yung authored Oct 02, 2020
  
  24f406e6
- Update legalizer-info-validation.mir test to test all opcodes. · 1e020b2a
  Amara Emerson authored Oct 02, 2020
  1e020b2a
- Revert "[WebAssembly] Emulate v128.const efficiently" · 432e4e56
  Stella Stamenova authored Oct 02, 2020
  432e4e56
- [AArch64] Generate dot for v16i8 sum reduction to i32 · f1925949
  Vinay Madhusudan authored Oct 02, 2020
  f1925949
- Fix interaction between stack alignment and inline-asm stack clash protection · f2c6bfa3
  serge-sans-paille authored Jul 23, 2020
  f2c6bfa3
- [Statepoints][ISEL] visitGCRelocate: chain to current DAG root. · 7b19cd06
  Denis Antrushin authored Oct 01, 2020
  7b19cd06
- [ARM] Prevent constants from iCmp instruction from being hoisted if part of a min(max()) pattern · f7c0e2b8
  Meera Nakrani authored Oct 02, 2020
  f7c0e2b8
- Fix limit behavior of dynamic alloca · 9573c9f2
  serge-sans-paille authored Sep 30, 2020
  9573c9f2
- [WebAssembly] Emulate v128.const efficiently · 542523a6
  Thomas Lively authored Oct 02, 2020
  542523a6
- [AArch64] Omit SEH directives for the epilogue if none are needed · afb4e0f2
  Martin Storsjö authored Oct 01, 2020
  afb4e0f2
- CodeGen: Fix livein calculation in MachineBasicBlock splitAt · 5136f474
  Carl Ritson authored Oct 02, 2020
  5136f474
- [PowerPC] Put the CR field in low bits of GRC during copying CRRC to GRC. · c4690b00
  Esme-Yi authored Oct 02, 2020
  c4690b00
- [XCOFF] Enable -fdata-sections on AIX · 78a9e62a
  jasonliu authored Oct 01, 2020
  78a9e62a
- [AArch64][SVE] Add lowering for llvm fabs · aab6f7db
  Muhammad Asif Manzoor authored Oct 01, 2020
  aab6f7db
- [GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs · 5402d11b
  Jessica Paquette authored Sep 30, 2020
  5402d11b
- [AArch64][GlobalISel] Use emitTestBit in selection for G_BRCOND · 8e8664e5
  Jessica Paquette authored Oct 01, 2020
  8e8664e5
- [AArch64][GlobalISel] Alias rules for G_FCMP to G_ICMP. · 017b8715
  Amara Emerson authored Oct 01, 2020
  017b8715
Oct 01, 2020
- [AArch64][GlobalISel] Make <8 x s8> integer arithmetic ops legal. · e28c5899
  Amara Emerson authored Oct 01, 2020
  
  e28c5899
- [AArch64][GlobalISel] Make <8 x s8> shifts legal and add selection support. · a97e97fa
  Amara Emerson authored Oct 01, 2020
  
  a97e97fa
- Revert "[AArch64][GlobalISel] Make <8 x s8> shifts legal." · 9a2b3bbc
  Amara Emerson authored Oct 01, 2020
  9a2b3bbc
- [AArch64][GlobalISel] Make <8 x s8> shifts legal. · 8071c2f5
  Amara Emerson authored Oct 01, 2020
  
  8071c2f5
- [AArch64][GlobalISel] Merge G_SHL, G_ASHR and G_LSHR legalizer rules together. · 9f6acb13
  Amara Emerson authored Oct 01, 2020
  9f6acb13
- [AArch64][GlobalISel] Use custom legalization for G_TRUNC for v8i8 vectors. · 73457536
  Amara Emerson authored Sep 23, 2020
  73457536
- [AArch64][GlobalISel] Camp oversize v4s64 G_FPEXT operations. · 4c265ce6
  Amara Emerson authored Oct 01, 2020
  
  4c265ce6