llvm-svn: 226302

llvm-svn: 226301

Add a utility script that executes an inferior process tucking its output away somewhere safe, and not letting error messages escape
This has potential to be useful in build automation environments

llvm-svn: 226300

llvm-svn: 226299

Part of <rdar://problem/17688758>

llvm-svn: 226298

llvm-svn: 226297

Similar to the unaligned cases.

Test was generated with update_llc_test_checks.py.

Part of <rdar://problem/17688758>

llvm-svn: 226296

llvm-svn: 226295

llvm-svn: 226294

llvm-svn: 226292

Raise the limit for column information from 8 bits to 16 bits.

llvm-svn: 226291

Line/column fixups already exist in `MDLocation`.  Delete the duplicated
logic in `DebugLoc`.

llvm-svn: 226290

llvm-svn: 226288

llvm-svn: 226287

llvm-svn: 226286

llvm-svn: 226285

llvm-svn: 226284

llvm-svn: 226283

llvm-svn: 226282

This patch makes File::parse() multi-thread safe. If one thread is running
File::parse(), other threads will block if they try to call the same method.
File::parse() is idempotent, so you can safely call  multiple times.

With this change, we don't have to wait for all worker threads to finish
in Driver::link(). Previously, Driver::link() calls TaskGroup::sync() to
wait for all threads running File::parse(). This was not ideal because
we couldn't start the resolver until we parse all files.

This patch increase parallelism by making Driver::link() to not wait for
worker threads. The resolver calls parse() to make sure that the file
being read has been parsed, and then uses the file. In this approach,
the resolver can run with the parser threads in parallel.

http://reviews.llvm.org/D6994

llvm-svn: 226281

llvm-svn: 226280

llvm-svn: 226279

Correct logic concerning 'T &&' deduction against lvalues.

llvm-svn: 226278

This patch disables target specific combine on X86ISD::INSERTPS dag nodes
if optlevel is CodeGenOpt::None.

The backend currently implements a target specific combine rule that converts
a vector load used by an INSERTPS dag node into a scalar load plus a
scalar_to_vector. This allows ISel to select a single INSERTPSrm instead of
two instructions (i.e. a vector load plus INSERTPSrr).

However, the existing target combine rule on INSERTPS nodes only works under
the assumption that ISel will always be able to match an INSERTPSrm. This is
not true in general at -O0, since the backend only allows folding a load into
the memory operand of an instruction if the optimization level is not
CodeGenOpt::None.

In the example below:

//
__m128 test(__m128 a, __m128 *b) {
  __m128 c = _mm_insert_ps(a, *b, 1 << 6);
  return c;
}
//

Before this patch, at -O0, the backend would have canonicalized the load to 'b'
into a scalar load plus scalar_to_vector. Later on, ISel would have selected an
INSERTPSrr leaving the insertps mask in an inconsistent state:

  movss 4(%rdi), %xmm1
  insertps  $64, %xmm1, %xmm0 # xmm0 = xmm1[1],xmm0[1,2,3].

With this patch, the backend avoids folding the vector load into the operand of
the INSERTPS. The new codegen at -O0 is:

  movaps (%rdi), %xmm1
  insertps  $64, %xmm1, %xmm0 # %xmm1[1],xmm0[1,2,3].

llvm-svn: 226277

Committed unreviewed with permission.

llvm-svn: 226276

Committed unreviewed with permission.

llvm-svn: 226275

The previous default behavior of LLD is --as-needed. LLD linked
against a DSO only if the DSO file was actually used to link an
executable (i.e. at least one symbol was resolved using the shared
library file.)

In this patch I added a boolean flag to FileNode for --as-needed.
I also added an accessor to DSO name to shared library file class.

llvm-svn: 226274

llvm-svn: 226273

llvm-svn: 226272

llvm-svn: 226271

Trying to debug a buildbot-only failure.

llvm-svn: 226270

llvm-svn: 226269

Wrong include order.

llvm-svn: 226268

llvm-svn: 226267

llvm-svn: 226266

These classes contain only abstract virtual functions. Explicit
constructors are redundant.

llvm-svn: 226265

The current 'big vectors' stack folded reload testing pattern is very bulky and makes it difficult to test all instructions as big vectors will tend to use only the ymm instruction implementations.

This patch changes the tests to use a nop call that lists explicit xmm registers as sideeffects, with this we can force a partial register spill of the relevant registers and then check that the reload is correctly folded. The asm generated only adds the forced spill, a nop instruction and a couple of extra labels (a fraction of the current approach).

More exhaustive tests will follow shortly, I've added some extra tests (the xmm versions of some of the existing folding tests) as a starting point.

Differential Revision: http://reviews.llvm.org/D6932

llvm-svn: 226264

llvm-svn: 226263

No functional changes.

llvm-svn: 226262

No functional changes.

llvm-svn: 226261