r200064 depends on r200051.

r200051 is broken: I tries to replace .mips_hack_elf_flags, which is a good
thing, but what it replaces it with is even worse.

The new emitMipsELFFlags it adds corresponds to no assembly directive, is not
marked as a hack and is not even printed to the .s file.

The patch also introduces more uses of hasRawTextSupport.

The correct way to remove .mips_hack_elf_flags is to have the mips target
streamer handle the default flags (and command line options). That way the
same code path is used for asm and obj. The streamer interface should *really*
correspond to what is printed in the .s file.

llvm-svn: 200078

llvm-svn: 200077

llvm-svn: 200076

Reduces the ARCMT migrator plist writer down to a single function,
arcmt::writeARCDiagsToPlist() which shares supporting functions with the
analyzer plist writer.

llvm-svn: 200075

a FunctionPass. With this change the loop vectorizer no longer is a loop
pass and can readily depend on function analyses. In particular, with
this change we no longer have to form a loop pass manager to run the
loop vectorizer which simplifies the entire pass management of LLVM.

The next step here is to teach the loop vectorizer to leverage profile
information through the profile information providing analysis passes.

llvm-svn: 200074

Before:
  Deleted &operator=(const Deleted &)&= default;
  Deleted &operator=(const Deleted &)&&= delete;

After:
  Deleted &operator=(const Deleted &)& = default;
  Deleted &operator=(const Deleted &)&& = delete;

llvm-svn: 200073

There are a couple of pieces:
 * some lazy-evaluation members that store info listed in a qSupported response
 * new method SendPacketsAndConcatenateResponses which is used for
   fetching fixed-size objects from the remote gdbserver by using multiple
   packets if necessary (first use will be to fetch shared-library XML files).

llvm-svn: 200072

llvm-svn: 200071

Fix EnforceSmallerThan to check !hasVectorTypes on the other type instead of this type to force this type to be scalar.

llvm-svn: 200070

GetU32 and GetU64, to use memcpy to copy bytes into a local buffer instead
of having a (uint64_t *) etc local variable, pointing to the address, and
dereferencing it.  If compiled on a CPU where data alignment is required 
(e.g. the LDM instruction on armv7) and we try to GetU64 out of a mmap'ed 
DWARF file, that 8 byte quantity may not be world aligned and the program
can get an unaligned memory access fault.

<rdar://problem/15849231> 

llvm-svn: 200069

qProcessInfo prints the cputype and cpusubtype in base16.

llvm-svn: 200068

the loops in a function, and teach LICM to work in the presance of
LCSSA.

Previously, LCSSA was a loop pass. That made passes requiring it also be
loop passes and unable to depend on function analysis passes easily. It
also caused outer loops to have a different "canonical" form from inner
loops during analysis. Instead, we go into LCSSA form and preserve it
through the loop pass manager run.

Note that this has the same problem as LoopSimplify that prevents
enabling its verification -- loop passes which run at the end of the loop
pass manager and don't preserve these are valid, but the subsequent loop
pass runs of outer loops that do preserve this pass trigger too much
verification and fail because the inner loop no longer verifies.

The other problem this exposed is that LICM was completely unable to
handle LCSSA form. It didn't preserve it and it actually would give up
on moving instructions in many cases when they were used by an LCSSA phi
node. I've taught LICM to support detecting LCSSA-form PHI nodes and to
hoist and sink around them. This may actually let LICM fire
significantly more because we put everything into LCSSA form to rotate
the loop before running LICM. =/ Now LICM should handle that fine and
preserve it correctly. The down side is that LICM has to require LCSSA
in order to preserve it. This is just a fact of life for LCSSA. It's
entirely possible we should completely remove LCSSA from the optimizer.

The test updates are essentially accomodating LCSSA phi nodes in the
output of LICM, and the fact that we now completely sink every
instruction in ashr-crash below the loop bodies prior to unrolling.

With this change, LCSSA is computed only three times in the pass
pipeline. One of them could be removed (and potentially a SCEV run and
a separate LoopPassManager entirely!) if we had a LoopPass variant of
InstCombine that ran InstCombine on the loop body but refused to combine
away LCSSA PHI nodes. Currently, this also prevents loop unrolling from
being in the same loop pass manager is rotate, LICM, and unswitch.

There is one thing that I *really* don't like -- preserving LCSSA in
LICM is quite expensive. We end up having to re-run LCSSA twice for some
loops after LICM runs because LICM can undo LCSSA both in the current
loop and the parent loop. I don't really see good solutions to this
other than to completely move away from LCSSA and using tools like
SSAUpdater instead.

llvm-svn: 200067

right after the space for it is allocated on the stack, instead of trying
to initialize it in all the different places in this method.  It's too easy
for another uninitialized code path to sneak in as it is written right now.

llvm-svn: 200066

This makes lib/Target/PowerPC EmitRawText free.

llvm-svn: 200065

No code changes. Just reassignment of test case files.

llvm-svn: 200064

This reverts commit r200058 and adds the using directive for
ARMTargetTransformInfo to silence two g++ overload warnings.

llvm-svn: 200062

llvm-svn: 200061

when the .html file is generated.

llvm-svn: 200060

llvm-svn: 200059

This commit caused -Woverloaded-virtual warnings. The two new
TargetTransformInfo::getIntImmCost functions were only added to the superclass,
and to the X86 subclass. The other targets were not updated, and the
warning highlighted this by pointing out that e.g. ARMTTI::getIntImmCost was
hiding the two new getIntImmCost variants.

We could pacify the warning by adding "using TargetTransformInfo::getIntImmCost"
to the various subclasses, or turning it off, but I suspect that it's wrong to
leave the functions unimplemnted in those targets. The default implementations
return TCC_Free, which I don't think is right e.g. for ARM.

llvm-svn: 200058

Previously, string literals were ignored in all logical expressions.  This
reduces it to only ignore in logical and expressions.

assert(0 && "error"); // No warning
assert(0 || "error"); // Warn

Fixes PR17565

llvm-svn: 200056

This will be extended as we fix issues in the current implementation.

llvm-svn: 200054

Rename "ec" to "EC", and rename some iterators.

Then fix whitespace using clang-format-diff.

(As requested in http://llvm-reviews.chandlerc.com/D2559)

Differential Revision: http://llvm-reviews.chandlerc.com/D2594

llvm-svn: 200053

llvm-svn: 200052

This patch uses a common MipsTargetSteamer interface for both 
MipsAsmPrinter and MipsAsmParser for recording default and commandline
driven directives that affect ELF header flags.

It has been noted that the .ll tests affected by this patch belong in
test/Codegen/Mips. I will move them in a separate patch.

Also, a number of directives do not get expressed by AsmPrinter in the 
resultant .s assembly such as setting the correct ASI. I have noted this
in the tests and they will be addressed in later patches.

llvm-svn: 200051

llvm-svn: 200050

Patch by Andrew MacPherson.

llvm-svn: 200049

llvm-svn: 200048

it later in GDBRemoteCommunication::StartDebugserverProcess and report
an error.
<rdar://problem/15820813> 

llvm-svn: 200047

The i8 type is not registered with any register class.
This causes a segmentation fault in MachineLICM::getRegisterClassIDAndCost.

The code selects the first type associated with register class FPR8,
which happens to be i8.
It uses this type (i8) to get the representative class pointer, which is 0.
It then uses this pointer to access a field, resulting in segmentation fault.

Since i8 type is not being used for printing any neon instruction
we can safely remove it.

llvm-svn: 200046

allow this, and we should warn on it, but it turns out that people were already
relying on this.

We should introduce a -Wgcc-compat warning for this if the attributes are known
to GCC, but we don't currently track enough information about attributes to do
so reliably.

llvm-svn: 200045

llvm-svn: 200044

It was redundant (since ARM mode is the default) and misleading since
(e.g.) Cortex-A15 would not satisfy the #ifdef but would be in ARM
mode regardless.

llvm-svn: 200043

llvm-svn: 200042

Adds a getSemanticSpelling function to semantic attribute subclasses which have a meaningful semantic spelling. Adds a sibling function to parsed attribtues (via AttributeList) for getting the semantic spelling, if one were to exist. This can be used for cleaner code that deals directly with the semantic spellings (such as the MSInheritance attribute).

llvm-svn: 200041

This allows llvm-ar to mmap the input files only once.

llvm-svn: 200040

llvm-svn: 200039

This change does not affect anything because everybody seems to be using
Object/COFF.h instead. But the definition is not for PE32 but for PE32+,
so fix it anyway.

llvm-svn: 200038

llvm-svn: 200037

Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before).

llvm-svn: 200036