Add more owners to CODE_OWNERS.TXT (Kostya Serebryany: AddressSanitizer and ThreadSanitizer; Evgeniy Stepanov: MemorySanitizer)

llvm-svn: 185064

llvm-svn: 185061

This is essentially reverting one piece of 184793 to try to fix one of Apple's
buildbots.  I will check with Eric to see if this is OK or if we need to find
some other solution.

llvm-svn: 185060

There are a few valid situation where we care about the structure inside a
directory, but not about the directory itself. A simple example is for unit
testing directory traversal.

PathV1 had a function like this, add one to V2 and port existing users of the
created temp file and delete it hack to using it.

llvm-svn: 185059

llvm-svn: 185052

When we store values for reversed induction stores we must not store the
reversed value in the vectorized value map. Another instruction might use this
value.

This fixes 3 test cases of PR16455.

llvm-svn: 185051

[APFloat] Added unittest for APFloat.divide that checks special cases, result categories, and result statuses.

llvm-svn: 185050

The Builtin attribute is an attribute that can be placed on function call site that signal that even though a function is declared as being a builtin,

rdar://problem/13727199

llvm-svn: 185049

llvm-svn: 185047

llvm-svn: 185045

[APFloat] Added unittest for APFloat.multiply that checks special cases, result categories, and result status.

llvm-svn: 185044

[APFloat] Added unittest for APFloat.subtract that checks special cases, result categories, and result status.

llvm-svn: 185043

SLP: When searching for vectorization opportunities scan the blocks in post-order because we grow chains upwards.

llvm-svn: 185041

SLP: Dont erase instructions during vectorization because it prevents the outerloops from iterating over the instructions.

llvm-svn: 185040

In InstCombine{AddSub,MulDivRem} convert APFloat.isFiniteNonZero() && !APFloat.isDenormal => APFloat.isNormal.

llvm-svn: 185037

Currently inside APFloat fcNormal still implies the old definition of Normal
(i.e. isFiniteNonZero) instead of the proper IEEE-754R definition that the
external method isNormal() uses.

This patch prepares for the internal switch inside APFloat by converting all
references that check if a category is fcNormal directly with an indirect call
via isFiniteNonZero().

llvm-svn: 185036

This reverts commit r185020

llvm-svn: 185032

Option groups don't have prefixes.  Option dumping is basically dead
code unless there is something wrong with the option table, so this
isn't an important crasher.

llvm-svn: 185031

llvm-svn: 185030

function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.

llvm-svn: 185026

ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is not used for incompatible calling conventions.

(Currently, ARM 'this'-returns are handled in the standard calling convention case by treating R0 as preserved and doing some extra magic in LowerCallResult; this may not apply to calling conventions added in the future so this patch provides and documents an interface for indicating such)

llvm-svn: 185024

No functionality change.
It should suffice to check the type of a debug info metadata, instead of
calling Verify.

llvm-svn: 185020

llvm-svn: 185016

llvm-svn: 185015

llvm-svn: 185012

subs.

llvm-svn: 185011

llvm-svn: 184974

llvm-svn: 184973

Patch by 罗勇刚(Yonggang Luo).

llvm-svn: 184971

llvm-svn: 184969

This allows for targeting the ARMv8 AArch32 variant.

llvm-svn: 184967

Do not add cse-ed instructions into the visited map because we dont want to consider them as a candidate for replacement of instructions to be visited.

llvm-svn: 184966

Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):

+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.

llvm-svn: 184965

The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.

llvm-svn: 184964

Make v4 the default ARM architecture attribute, to match CodeGen.

llvm-svn: 184962

llvm-svn: 184960

llvm-svn: 184955

llvm itself is now PathV1 clean.

llvm-svn: 184947

[PowerPC] Accept 17-bit signed immediates for addis

The assembler currently strictly verifies that immediates for
s16imm operands are in range (-32768 ... 32767).  This matches
the behaviour of the GNU assembler, with one exception: gas
allows, as a special case, operands in an extended range
(-65536 .. 65535) for the addis instruction only (and its
extended mnemonic lis).

The main reason for this seems to be to allow using unsigned
16-bit operands for lis, e.g. like lis %r1, 0xfedc.

Since this has been supported by gas for a long time, and
assembler source code seen "in the wild" actually exploits
this feature, this patch adds equivalent support to LLVM
for compatibility reasons.

llvm-svn: 184946

[PowerPC] Support symbolic u16imm operands

Currently, all instructions taking s16imm operands support symbolic
operands.  However, for u16imm operands, we only support actual
immediate integers.  This causes the assembler to reject code like

  ori %r5, %r5, symbol@l

This patch changes the u16imm operand definition to likewise
accept symbolic operands.  In fact, s16imm and u16imm can
share the same encoding routine, now renamed to getImm16Encoding.

llvm-svn: 184944