Commits · 2759cfa0c35478b5a3bc1e51a1ed817d1b1dc39f · Roger Ferrer / llvm-epi · GitLab

Jan 19, 2024
- [AMDGPU] Remove unnecessary add instructions in ctlz.i8 (#77615) · 2759cfa0
  Leon Clark authored Jan 19, 2024
  2759cfa0
- [RISCV] Don't look through EXTRACT_ELEMENT in lowerScalarInsert if the element... · 0ad83bc2
  Craig Topper authored Jan 18, 2024
  0ad83bc2
- [NFC][PowerPC] remove the redundant spill related flags setting · 1f615074
  Chen Zheng authored Jan 18, 2024
  
  1f615074
- Revert "[BOLT] Fix unconditional output of boltedcollection in merge-fdata (#78653)" · 9fec33aa
  Amir Ayupov authored Jan 18, 2024
  9fec33aa
- [BOLT] Fix unconditional output of boltedcollection in merge-fdata (#78653) · 82bc33ea
  Amir Ayupov authored Jan 18, 2024
  82bc33ea
- [RISCV] Key VectorIntrinsicCostTable by SEW [nfc-ish] · 8bf624af
  Philip Reames authored Jan 18, 2024
  8bf624af
- [RISCV] Add statistic support for VSETVL insertion pass (#78543) · 20a3484b
  Piyou Chen authored Jan 19, 2024
  20a3484b
- [RISCV] Add support for new unprivileged extensions defined in profiles spec (#77458) · 86493280
  Luke Lau authored Jan 19, 2024
  86493280
Jan 18, 2024
- [X86] Fix RTTI proxy emission for 32-bit (#78622) · 741b8363
  Shoaib Meenai authored Jan 18, 2024
  741b8363
- [Hexagon] Flip subreg bit for reverse pairs hvx .new (#75873) · 96542c01
  quic-akaryaki authored Jan 18, 2024
  96542c01
- [RISCV] Adjust select shuffle cost to reflect mask creation cost (#77963) · 2663d2cb
  Philip Reames authored Jan 18, 2024
  2663d2cb
- [NVPTX][NFC] Remove unused parameter of getArgumentAlignment (#78604) · 0c195e50
  Alex MacLean authored Jan 18, 2024
  
  0c195e50
- [SystemZ] i128 cost model (#78528) · 964565f4
  Jonas Paulsson authored Jan 18, 2024
  964565f4
- [SPIR-V] improve performance of Module Analysis stage in the part of... · 774b9577
  Vyacheslav Levytskyy authored Jan 18, 2024
  774b9577
- [X86][MC] Fix wrong encoding of promoted BMI instructions due to missing NoCD8 (#78386) · d124b022
  XinWang10 authored Jan 18, 2024
  d124b022
- [X86] Fix failures on EXPENSIVE_CHECKS builds · 8bc7c0a0
  Shengchen Kan authored Jan 19, 2024
  8bc7c0a0
- [X86] X86MCInstLower.cpp - fix spelling mistake · 110e1717
  Simon Pilgrim authored Jan 18, 2024
  
  110e1717
- [X86] Emit verbose (constant) comments before EVEX compression tag (#78585) · 33287e35
  Simon Pilgrim authored Jan 18, 2024
  33287e35
- [AMDGPU] Add global_load_tr for GFX12 (#77772) · 57f6a3f7
  Piotr Sobczak authored Jan 18, 2024
  57f6a3f7
- [AMDGPU] Update uses of new VOP2 pseudos for GFX12 (#78155) · 0a3a0ea5
  Jay Foad authored Jan 18, 2024
  0a3a0ea5
- [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (#75917) · 3e6589f2
  Mariusz Sikora authored Jan 18, 2024
  3e6589f2
- AMDGPU/GFX12: Add new dot4 fp8/bf8 instructions (#77892) · 28b7e498
  Mariusz Sikora authored Jan 18, 2024
  28b7e498
- [X86] Add X86::getConstantFromPool helper function to replace duplicate implementations. · d12dffac
  Simon Pilgrim authored Jan 18, 2024
  d12dffac
- [AMDGPU] Fix -Wunused-variable in SIInsertWaitcnts.cpp (NFC) · 779af9b7
  Jie Fu authored Jan 18, 2024
  779af9b7
- [AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438) · ba52f06f
  Jay Foad authored Jan 18, 2024
  ba52f06f
- [AMDGPU] Work around s_getpc_b64 zero extending on GFX12 (#78186) · 9ca36932
  Jay Foad authored Jan 18, 2024
  
  9ca36932
- [AMDGPU] Allow potentially negative flat scratch offsets on GFX12 (#78193) · c111dc72
  Jay Foad authored Jan 18, 2024
  c111dc72
- [AArch64][SME] Conditionally do smstart/smstop (#77113) · 51e3d2f7
  Matthew Devereau authored Jan 18, 2024
  51e3d2f7
- [RISCV] Vectorize phi for loop carried @llvm.vector.reduce.fadd (#78244) · 15b0fabb
  Luke Lau authored Jan 18, 2024
  15b0fabb
- [AMDGPU][True16] Support V_FLOOR_F16. (#78446) · 2a869ced
  Ivan Kosarev authored Jan 18, 2024
  
  2a869ced
- [AMDGPU] Add mark last scratch load pass (#75512) · 1d286ad5
  Mirko Brkušanin authored Jan 18, 2024
  
  1d286ad5
- [AMDGPU][NFC] Rename feature FP8Insts to FP8ConversionInsts (#78439) · 264fd9e1
  Mariusz Sikora authored Jan 18, 2024
  
  264fd9e1
- [AMDGPU] Use alias info to relax waitcounts for LDS DMA (#74537) · 021def6c
  Stanislav Mekhanoshin authored Jan 17, 2024
  021def6c
- Recommit "[RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension." (#76785) · ba81477e
  Chia authored Jan 18, 2024
  ba81477e
- [X86] Support lowering for APX promoted BMI instructions. (#77433) · 2d92f7de
  XinWang10 authored Jan 17, 2024
  2d92f7de
- [AMDGPU] Reapply 'Sign extend simm16 in setreg intrinsic' (#78492) · 558ea411
  Stanislav Mekhanoshin authored Jan 17, 2024
  558ea411
- [NVPTX] extend type support for nvvm.{min,max,mulhi,sad} (#78385) · 430a40d1
  Alex MacLean authored Jan 17, 2024
  430a40d1
- [RISCV] Add LUI/AUIPC+ADDI fusions to sifive-p450. (#78501) · f2b5a314
  Craig Topper authored Jan 17, 2024
  
  f2b5a314
- [X86] Don't respect large data threshold for globals with an explicit section (#78348) · 00647a18
  Arthur Eubanks authored Jan 17, 2024
  00647a18
Jan 17, 2024
- [AArch64] Improve cost computations for odd vector mem ops. (#78181) · e473daa7
  Florian Hahn authored Jan 17, 2024
  e473daa7