Commits · 283b4d6ba3119730e1722e8d78974b2c29d2492a · Roger Ferrer / llvm-epi · GitLab

Oct 08, 2020
- [GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions. · 283b4d6b
  Amara Emerson authored Oct 02, 2020
  283b4d6b
- [AMDGPU] Add patterns for mad/mac legacy f32 instructions · 7238faa4
  Jay Foad authored Oct 06, 2020
  7238faa4
- [AIX] add new option -mignore-xcoff-visibility · 92bca128
  diggerlin authored Oct 08, 2020
  92bca128
- AArch64: treat MC expressions as 2s complement arithmetic. · 38348fa2
  Tim Northover authored Sep 22, 2020
  38348fa2
- [AMDGPU] Prefer SplitVectorLoad/Store over expandUnalignedLoad/Store · 7c88d13f
  Mirko Brkusanin authored Oct 06, 2020
  7c88d13f
- [AMDGPU] Add test with redundant copies to temporary stack slot produced by expandUnalignedLoad · 380087e6
  Mirko Brkusanin authored Oct 06, 2020
  380087e6
- [ARM] Replace llvm.experimental.vector.reduce.smax with llvm.vector.reduce.smax. NFC · 81b4f338
  David Green authored Oct 08, 2020
  81b4f338
- BPF: fix incorrect DAG2DAG load optimization · 31611721
  Yonghong Song authored Oct 07, 2020
  31611721
- [X86] Fix bug in -mlvi-cfi that may clobber a live register · ad4313fc
  Scott Constable authored Oct 07, 2020
  ad4313fc
- [ImplicitNullChecks] Support complex addressing mode · 35cb45c5
  Anna Thomas authored Sep 24, 2020
  35cb45c5
- [X86] Defer the creation of LCMPXCHG16B_SAVE_RBX until finalize-isel · 68e1a8d2
  Craig Topper authored Oct 07, 2020
  68e1a8d2
Oct 07, 2020
- [BasicBlockSections] Make sure that the labels for address-taken blocks are... · 34cd06a9
  Rahman Lavaee authored Oct 07, 2020
  34cd06a9
- [SVE] Add legalisation tests to sve-fixed-length-fp-reduce.ll · 365ef499
  Cameron McInally authored Oct 07, 2020
  
  365ef499
- [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. · 322d0afd
  Amara Emerson authored Oct 02, 2020
  322d0afd
- [WebAssembly] Rename Emscripten EH functions · 3bba91f6
  Heejin Ahn authored Sep 28, 2020
  3bba91f6
- BPF: add AdjustOpt IR pass to generate verifier friendly codes · ddf1864a
  Yonghong Song authored Aug 06, 2020
  ddf1864a
- [AMDGPU] Support disassembly for AMDGPU kernel descriptors · 528057c1
  Ronak Chauhan authored Oct 07, 2020
  528057c1
- [SVE] Lower fixed length VECREDUCE_OR operation · 333b2ab6
  Cameron McInally authored Oct 07, 2020
  333b2ab6
- [AMDGPU] Implement hardware bug workaround for image instructions · f71f5f39
  Rodrigo Dominguez authored Apr 03, 2020
  f71f5f39
- [ARM] Regenerate vldlane tests · 6625892d
  Simon Pilgrim authored Oct 07, 2020
  6625892d
- [SDag] SimplifyDemandedBits: simplify to FP constant if all bits known · 1aa8e6a5
  Jay Foad authored Sep 30, 2020
  1aa8e6a5
- BPF: avoid duplicated globals for CORE relocations · edd71db3
  Yonghong Song authored Oct 06, 2020
  edd71db3
- [CodeGen][TailDuplicator] Don't duplicate blocks with INLINEASM_BR · d2c61d2b
  Bill Wendling authored Oct 06, 2020
  d2c61d2b
Oct 06, 2020
- [BPF][NewPM] Make BPFTargetMachine properly adjust NPM optimizer pipeline · 40251fee
  Arthur Eubanks authored Oct 05, 2020
  40251fee
- [ARM] Fold select_cc(vecreduce_[u|s][min|max], x) into VMINV or VMAXV · 68e002e1
  Sam Tebbs authored Sep 23, 2020
  68e002e1
- [Statepoints] Change statepoint machine instr format to better suit VReg lowering. · c08d48fc
  Denis Antrushin authored Sep 05, 2020
  c08d48fc
- [SVE] Lower fixed length vector fneg and fsqrt operations. · 27f3d51b
  Paul Walker authored Oct 01, 2020
  27f3d51b
- [SVE] Lower fixed length vector floating point rounding operations. · 8bb702a8
  Paul Walker authored Oct 01, 2020
  8bb702a8
- [SVE][CodeGen] Fix DAGCombiner::ForwardStoreValueToDirectLoad for scalable vectors · 4ed47d50
  David Sherwood authored Sep 03, 2020
  4ed47d50
- Fix reordering of instructions during VirtRegRewriter unbundling · ea9d6392
  Carl Ritson authored Oct 06, 2020
  ea9d6392
Oct 05, 2020
- [SelectionDAG] Make sure FMF are propagated when getSetcc canonicalizes FP constants to RHS. · 1127662c
  Craig Topper authored Oct 05, 2020
  1127662c
- [SVE] Add legalisation tests to sve-fixed-length-int-reduce.ll · 6bec45e2
  Cameron McInally authored Oct 05, 2020
  
  6bec45e2
- [SVE][CodeGen] Fix TypeSize/ElementCount related warnings in sve-split-store.ll · fa029308
  David Sherwood authored Aug 26, 2020
  fa029308
- [GlobalISel] Fix CSEMIRBuilder silently allowing use-before-def. · c2bce848
  Amara Emerson authored Sep 29, 2020
  c2bce848
- Revert "[ARM]Fold select_cc(vecreduce_[u|s][min|max], x) into VMINV or VMAXV" · c9f5cdd4
  Amara Emerson authored Oct 05, 2020
  c9f5cdd4
- [SelectionDAG] Don't remove unused negated constant immediately · b326d4ff
  Qiu Chaofan authored Oct 06, 2020
  b326d4ff
- [SVE] Lower fixed length VECREDUCE_AND operation · 9642ded8
  Cameron McInally authored Oct 05, 2020
  9642ded8
- [ARM]Fold select_cc(vecreduce_[u|s][min|max], x) into VMINV or VMAXV · 2573cf3c
  Sam Tebbs authored Sep 23, 2020
  2573cf3c
- [AMDGPU][RegAlloc][SplitKit] Pre-commit test for D88821 · 707c3d4d
  Carl Ritson authored Oct 05, 2020
  
  707c3d4d
- [VE] Support register and frame-index pair correctly · 5b5e78a4
  Kazushi (Jam) Marukawa authored Sep 21, 2020
  5b5e78a4