llvm-svn: 19799

llvm-svn: 19798

llvm-svn: 19797

all.  This should speed up the X86 backend fairly significantly on integer
codes.  Now if only we didn't have to compute livevar still... ;-)

llvm-svn: 19796

registers.  This information is computed directly by the register allocator
now.

llvm-svn: 19795

llvm-svn: 19794

llvm-svn: 19793

llvm-svn: 19792

llvm-svn: 19791

llvm-svn: 19789

it.

llvm-svn: 19788

llvm-svn: 19787

llvm-svn: 19786

llvm-svn: 19782

The first half of correct chain insertion for libcalls. This is not enough
to fix Fhourstones yet though.

llvm-svn: 19781

the new TLI that is available.

Implement support for handling out of range shifts.  This allows us to
compile this code (a 64-bit rotate):

unsigned long long f3(unsigned long long x) {
  return (x << 32) | (x >> (64-32));
}

into this:

f3:
        mov %EDX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        ret

GCC produces this:

$ gcc t.c -masm=intel -O3 -S -o - -fomit-frame-pointer
..
f3:
        push    %ebx
        mov     %ebx, DWORD PTR [%esp+12]
        mov     %ecx, DWORD PTR [%esp+8]
        mov     %eax, %ebx
        mov     %edx, %ecx
        pop     %ebx
        ret

The Simple ISEL produces (eww gross):

f3:
        sub %ESP, 4
        mov DWORD PTR [%ESP], %ESI
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %ECX, DWORD PTR [%ESP + 12]
        mov %EAX, 0
        mov %ESI, 0
        or %EAX, %ECX
        or %EDX, %ESI
        mov %ESI, DWORD PTR [%ESP]
        add %ESP, 4
        ret

llvm-svn: 19780

llvm-svn: 19779

llvm-svn: 19778

llvm-svn: 19777

llvm-svn: 19776

doesn't support certain directives and symbols on cygwin are prefixed with
an underscore. This patch makes the necessary adjustments to the output.

llvm-svn: 19775

llvm-svn: 19774

llvm-svn: 19773

llvm-svn: 19772

Delete dead functions.

llvm-svn: 19771

Also, make DiffFilesWithTolerance take sys::Path objects instead of std::strings.

llvm-svn: 19770

llvm-svn: 19769

llvm-svn: 19768

used by other tools.

llvm-svn: 19767

llvm-svn: 19766

llvm-svn: 19765

llvm-svn: 19764

llvm-svn: 19763

won't be propagated to the configure script until there's a need to change
configure.ac for some larger purpose.

llvm-svn: 19762

llvm-svn: 19761

differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all.  On the X86,
this turns this code:

    switch (MI->getOpcode()) {
    case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
    case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
    case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
    case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
    }

into this:

    switch (MI->getOpcode()) {
    case X86::ADC32mi:
    case X86::ADC32mr:
    case X86::ADD32mi:
    case X86::ADD32mr:
    case X86::AND32mi:
    case X86::AND32mr:
    case X86::CMP32mi:
    case X86::CMP32mr:
    case X86::MOV32mi:
    case X86::MOV32mr:
    case X86::OR32mi:
    case X86::OR32mr:
    case X86::SBB32mi:
    case X86::SBB32mr:
    case X86::SHLD32mrCL:
    case X86::SHRD32mrCL:
    case X86::SUB32mi:
    case X86::SUB32mr:
    case X86::TEST32mi:
    case X86::TEST32mr:
    case X86::XCHG32mr:
    case X86::XOR32mi:
    case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::ADC32mi8:
    case X86::ADD32mi8:
    case X86::AND32mi8:
    case X86::OR32mi8:
    case X86::ROL32mi:
    case X86::ROR32mi:
    case X86::SAR32mi:
    case X86::SBB32mi8:
    case X86::SHL32mi:
    case X86::SHR32mi:
    case X86::SUB32mi8:
    case X86::TEST8mi:
    case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
    }

After this, the generated asmwriters look pretty much as though they were
generated by hand.  This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.

llvm-svn: 19760

strings starts out with a constant string, we emit the string first, using
a table lookup (instead of a switch statement).

Because this is usually the opcode portion of the asm string, the differences
between the instructions have now been greatly reduced.  This allows many
more case statements to be grouped together.

This patch also allows instruction cases to be grouped together when the
instruction patterns are exactly identical (common after the opcode string
has been ripped off), and when the differing operand is a MachineInstr
operand that needs to be formatted.

The end result of this is a mean and lean generated AsmPrinter!

llvm-svn: 19759

llvm-svn: 19758

llvm-svn: 19757

llvm-svn: 19756