Commits · 3b5456d5f0d1fbfcdf6f6a18e9adec5e42a560ee · Roger Ferrer / llvm-epi · GitLab

May 31, 2022
- [RISCV][NFC] Adjust some comments in RISCVInsertVSETVLI · 5a2e640e
  Fraser Cormack authored May 31, 2022
  5a2e640e
- [RISCV] Pass OptLevel to `RISCVDAGToDAGISel` correctly · 2cadf84f
  eopXD authored May 30, 2022
  2cadf84f
May 30, 2022
- [RISCV] isel (add (and X, 0x1FFFFFFFE), Y) as (SH1ADD (SRLI X, 1), Y) · 6a6cf2e2
  Craig Topper authored May 29, 2022
  6a6cf2e2
May 28, 2022
- [RISCV] Allow PRE of vsetvli involving non-1 LMUL · 85b44700
  Philip Reames authored May 27, 2022
  85b44700
May 27, 2022
- [RISCV] Use template version of SignExtend64 for constant extends. NFC · b09e5454
  Craig Topper authored May 27, 2022
  b09e5454
- [RISCV] Remove unused variables. NFC · d0f65eaa
  Craig Topper authored May 27, 2022
  
  d0f65eaa
- [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. · aaad5075
  Craig Topper authored May 27, 2022
  aaad5075
- [RISCV][NFC] Unify compatibility checks under one function · 3e450d9c
  Fraser Cormack authored May 26, 2022
  3e450d9c
- [RISCV] Simplify code after D125905 · cef377d7
  Fangrui Song authored May 26, 2022
  
  cef377d7
- [RISCV] Add a subtarget feature to enable unaligned scalar loads and stores · 8a3b6ba7
  Philip Reames authored May 26, 2022
  8a3b6ba7
May 26, 2022
- [RISCV] Simplfy creation of IndexVT in lowerMaskedGather/lowerMaskedScatter. NFC · e9ac99b6
  Craig Topper authored May 26, 2022
  e9ac99b6
- [RISCV] reorganize getFrameIndexReference to reduce code duplication [nfc] · d58cc083
  Philip Reames authored May 26, 2022
  d58cc083
- [RISCV] Allow compatible VTYPE in AVL Reg Forward cases · afe49934
  Philip Reames authored May 26, 2022
  afe49934
- [RISCV][NFC] Add braces to 'else' to match braced 'if' · 2c9983f5
  Fraser Cormack authored May 26, 2022
  
  2c9983f5
- [RISCV] Fix state persistence bugs (PR55548) · e45087fd
  Kito Cheng authored May 20, 2022
  e45087fd
- [RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op. · b271488e
  Jianjian GUAN authored May 11, 2022
  b271488e
May 25, 2022
- Reapply "[RISCV] Enable strict assertions in InsertVSETVLI data flow" · 1f06398e
  Philip Reames authored May 25, 2022
  1f06398e
- [riscv] Remove mutation of prior vsetvli from insertion dataflow · be2cb824
  Philip Reames authored May 25, 2022
  be2cb824
- [RISCV] Preserve fast math flags in lowerVPOp. · 172149e9
  Craig Topper authored May 25, 2022
  172149e9
- [RISCV] Hoist VSETVLI vlmax, vtype out of scalable loops · 2a3b6f2c
  Philip Reames authored May 25, 2022
  2a3b6f2c
- [RISCV] Restructure comment and add clarifying assert to getFrameIndexReference [NFC] · dd336b68
  Philip Reames authored May 25, 2022
  dd336b68
- [RISCV] Add pre-emit pass to make more instructions compressible · 29a5a7c6
  Lewis Revill authored Apr 25, 2022
  29a5a7c6
- [RISCV] Fix vnsrl/vnsra isel patterns that are dropping VL. · 66db5312
  Craig Topper authored May 24, 2022
  66db5312
- [RISCV] Replace untested code with assert · fd937366
  Fraser Cormack authored May 24, 2022
  fd937366
- [RISCV] Ensure the forwarded AVL register is alive · 948d9313
  Philip Reames authored May 24, 2022
  948d9313
May 24, 2022
- [RISCV] Add an operand kind to the opcode/imm returned from RISCVMatInt. · d2ee2c9c
  Craig Topper authored May 24, 2022
  d2ee2c9c
- [riscv] Use getFirstInstrTerminator [nfc] · fb948572
  Philip Reames authored May 24, 2022
  
  fb948572
- [RISCV] Hoist VSETVLI out of idiomatic fixed length vector loops · a95ecb20
  Philip Reames authored May 24, 2022
  a95ecb20
- Recommit "[RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates." · 415b9f59
  Craig Topper authored May 24, 2022
  415b9f59
- [RISCV] Ensure the entire stack is aligned to the RVV stack alignment · 08c9fb84
  Fraser Cormack authored May 19, 2022
  08c9fb84
- [RISCV] Fix RVV stack frame alignment bugs · cb8681a2
  Fraser Cormack authored May 16, 2022
  cb8681a2
May 23, 2022
- [LV] Improve register pressure estimate at high VFs · ade47bdc
  Peter Waller authored May 16, 2022
  ade47bdc
May 22, 2022
- [SVE] Enable use of 32bit gather/scatter indices for fixed length vectors · 258dac43
  Paul Walker authored Apr 28, 2022
  258dac43
May 20, 2022
- [RISCV] Fix logic for determining RVV stack padding · d60ae47f
  Fraser Cormack authored May 19, 2022
  d60ae47f
- [RISCV] Add VL patterns for vector widening floating-point fused multiply-add instructions. · 8fc4fcec
  Jianjian GUAN authored Apr 27, 2022
  8fc4fcec
May 19, 2022
- Revert "[RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates." · dfe513ae
  Craig Topper authored May 19, 2022
  dfe513ae
- [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf · 6bec3e93
  Jay Foad authored Oct 06, 2021
  6bec3e93
- [NFC][RISCV] Enable TuneNoDefaultUnroll feature to control targets which use... · 861489af
  Zi Xuan Wu (Zeson) authored May 19, 2022
  861489af
May 18, 2022
- [RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates. · 86f7d707
  Craig Topper authored May 18, 2022
  86f7d707
- Revert "[RISCV] Enable strict assertions in InsertVSETVLI data flow" · d4545e6f
  Philip Reames authored May 17, 2022
  d4545e6f