- Apr 11, 2013
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Benjamin Kramer authored
llvm-svn: 179277
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Benjamin Kramer authored
llvm-svn: 179276
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Benjamin Kramer authored
llvm-svn: 179275
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Benjamin Kramer authored
Rename the C function to create a SLPVectorizerPass to something sane and expose it in the header file. llvm-svn: 179272
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Michael Liao authored
As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane, vector select could be simplified to AND/OR or removed if one or both values being selected is all 0s or all 1s. llvm-svn: 179267
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Michael Liao authored
As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
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Michael Liao authored
This patch is revised based on patch from Victor Umansky <victor.umansky@intel.com>. More cases are handled in X86's bool simplification, i.e. - SETCC_CARRY - value is truncated to i1 with AND As a by-product, PR5443 is also fixed. llvm-svn: 179265
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NAKAMURA Takumi authored
llvm-svn: 179263
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NAKAMURA Takumi authored
llvm-svn: 179262
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Rafael Espindola authored
llvm-svn: 179259
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Rafael Espindola authored
The object was already checked in, but was not being tested. llvm-svn: 179256
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Rafael Espindola authored
It was returning the loaded address of the section containing the relocation, which really doesn't seem to be the intent of this function. llvm-svn: 179255
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Hal Finkel authored
Because of how predication in implemented on PPC (only for branches), I think that this is the right thing to do. No functionality change intended. llvm-svn: 179252
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Daniel Dunbar authored
llvm-svn: 179249
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Daniel Dunbar authored
llvm-svn: 179248
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Daniel Dunbar authored
llvm-svn: 179247
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Nico Rieck authored
llvm-svn: 179244
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Daniel Dunbar authored
llvm-svn: 179243
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Eli Bendersky authored
llvm-svn: 179241
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Nico Rieck authored
Add support for the COFF relocation types IMAGE_REL_I386_DIR32NB and IMAGE_REL_AMD64_ADDR32NB for 32- and 64-bit respectively. These are similar to normal 4-byte relocations except that they do not include the base address of the image. Image-relative relocations are used for debug information (32-bit) and SEH unwind tables (64-bit). A new MCSymbolRef variant called 'VK_COFF_IMGREL32' is introduced to specify such relocations. For AT&T assembly, this variant can be accessed using the symbol suffix '@imgrel'. llvm-svn: 179240
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Joey Gouly authored
llvm-svn: 179239
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Hal Finkel authored
In the simple and triangle if-conversion cases, when CopyAndPredicateBlock is used because the to-be-predicated block has other predecessors, we need to explicitly remove the old copied block from the successors list. Normally if conversion relies on TII->AnalyzeBranch combined with BB->CorrectExtraCFGEdges to cleanup the successors list, but if the predicated block contained an un-analyzable branch (such as a now-predicated return), then this will fail. These extra successors were causing a problem on PPC because it was causing later passes (such as PPCEarlyReturm) to leave dead return-only basic blocks in the code. llvm-svn: 179227
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Bill Wendling authored
llvm-svn: 179226
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Jack Carter authored
These changes are based on commit responses for r179135. llvm-svn: 179225
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- Apr 10, 2013
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Bill Wendling authored
llvm-svn: 179224
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Kay Tiong Khoo authored
llvm-svn: 179223
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Eric Christopher authored
temporarily while we work on plumbing through some changes to continue supporting gdb on darwin. This reverts commit r179122. llvm-svn: 179222
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Bill Wendling authored
Compact unwind has an encoding for when we're not able to generate compact unwind and must generate an EH frame instead. Track that, but still emit that CU encoding. llvm-svn: 179220
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Kay Tiong Khoo authored
llvm-svn: 179215
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Benjamin Kramer authored
This avoids a nasty const correctness issue (AnalysisIDs are const, Pass* isn't). llvm-svn: 179213
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Bill Wendling authored
If anyone objects please let me know. llvm-svn: 179212
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Preston Gurd authored
In the X86 back end, getMemoryOperandNo() returns the offset into the operand array of the start of the memory reference descriptor. Additional code in EncodeInstruction provides an additional adjustment. This patch places that additional code in a separate function, called getOperandBias, so that any caller of getMemoryOperandNo can also call getOperandBias. llvm-svn: 179211
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Chad Rosier authored
wasn't always the start of the operand. If there was a symbol reference, then Start pointed to that token. It's very likely there are other places that need to be updated. llvm-svn: 179210
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Jyotsna Verma authored
to disable following tests for Hexagon that require direct object generation support. DebugInfo/dwarf-public-names.ll DebugInfo/dwarf-version.ll DebugInfo/member-pointers.ll DebugInfo/namespace.ll DebugInfo/two-cus-from-same-file.ll Fixes bug 15616 - http://llvm.org/bugs/show_bug.cgi?id=15616 llvm-svn: 179209
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Nadav Rotem authored
Make the SLP store-merger less paranoid about function calls. We check for function calls when we check if it is safe to sink instructions. llvm-svn: 179207
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Nadav Rotem authored
llvm-svn: 179206
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Chad Rosier authored
llvm-svn: 179205
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Hal Finkel authored
I've not seen this happen in practice, and probably can't until we start allowing decrement-counter-based conditional branches to be double predicated, but just in case, don't allow predication of a diamond in which both sides have ctr-defining branches. Even though the branching behavior of these can be predicated, the counter-decrementing behavior cannot be. llvm-svn: 179199
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Chad Rosier authored
Test cases that regressed due to r179115, plus a few more, were added in r179182. Original commit message below: [ms-inline asm] Use parsePrimaryExpr in lieu of parseExpression if we need to parse an identifier. Otherwise, parseExpression may parse multiple tokens, which makes it impossible to properly compute an immediate displacement. An example of such a case is the source operand (i.e., [Symbol + ImmDisp]) in the below example: __asm mov eax, [Symbol + ImmDisp] Part of rdar://13611297 llvm-svn: 179187
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Michel Danzer authored
21 more little piglits with radeonsi. Reviewed-by:
Tom Stellard <thomas.stellard@amd.com> llvm-svn: 179186
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