Commits · 4bb2eb15d4da76d880f8920f1f5fa94204a23eb0 · Roger Ferrer / llvm-epi · GitLab

Jan 15, 2012
- FileCheck-ize a test, make it more specific to directly test the shift · 4bb2eb15
  Chandler Carruth authored Jan 15, 2012
  4bb2eb15
- Remove SetWorkingDirectory from the Process interface. Nothing in LLVM · da22f30e
  Chandler Carruth authored Jan 15, 2012
  da22f30e
- Remove dead code. · fdcd669b
  David Blaikie authored Jan 15, 2012
  fdcd669b
- Truncate of undef is just undef of smaller size. · 201c1a35
  Craig Topper authored Jan 15, 2012
  201c1a35
Jan 14, 2012
- Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem. · c10e1aba
  Craig Topper authored Jan 14, 2012
  c10e1aba
- Add a bunch of AVX instructions to the folding tables. Also fixed the... · d78429f8
  Craig Topper authored Jan 14, 2012
  d78429f8
- Speculatively revert commit 148175 (rafael), to see if this fixes · 90212bde
  Duncan Sands authored Jan 14, 2012
  90212bde
- Fix a corner case hit by redundant phi elimination running after LSR. · 23ef0d6c
  Andrew Trick authored Jan 14, 2012
  23ef0d6c
- Only emit the Leh_func_endN symbol when needed. · dfde7631
  Rafael Espindola authored Jan 14, 2012
  dfde7631
- misched: Initial code for building an MI level scheduling DAG · 59ac4fb7
  Andrew Trick authored Jan 14, 2012
  59ac4fb7
- Move physreg dependency generation into aptly named addPhysRegDeps. · dbee9d89
  Andrew Trick authored Jan 14, 2012
  dbee9d89
- misched: Added ScheduleDAGInstrs::IsPostRA · 1d028a36
  Andrew Trick authored Jan 14, 2012
  1d028a36
- misched: Invoke the DAG builder on each sequence of schedulable instructions. · 7e120f4e
  Andrew Trick authored Jan 14, 2012
  7e120f4e
- Move things around to make the file navigable, even though it will probably be split up later. · 6344087e
  Andrew Trick authored Jan 14, 2012
  6344087e
- After r147827 and r147902, it's now possible for unallocatable registers to be · 6bb95253
  Evan Cheng authored Jan 14, 2012
  6bb95253
- Fix pasto from r146196. · 71a185c5
  Chad Rosier authored Jan 14, 2012
  71a185c5
- Cleanup test case by adding checks for test names. · d027d528
  Chad Rosier authored Jan 14, 2012
  d027d528
- Add TRI::getCallPreservedMask() hook. · b3c18a69
  Jakob Stoklund Olesen authored Jan 14, 2012
  b3c18a69
- Fix an unused variable warning that Chad noticed. · 4cf362ac
  Dan Gohman authored Jan 14, 2012
  4cf362ac
- Add a test showing how the Leh_func_endN symbol is used. · 78a6477b
  Rafael Espindola authored Jan 14, 2012
  78a6477b
- Remove previous commit while I debug the bot failures. · a6931287
  Rafael Espindola authored Jan 13, 2012
  a6931287
Jan 13, 2012
- Use RegisterTuples to generate pseudo-registers. · 35545421
  Jakob Stoklund Olesen authored Jan 13, 2012
  35545421
- Remove label that is not used anymore. · cef42c30
  Rafael Espindola authored Jan 13, 2012
  cef42c30
- Speculatively revert r148132+r148133 to try and fix a buildbot failure. · d476fdc3
  Eli Friedman authored Jan 13, 2012
  d476fdc3
- Skip the NAME field when forming tuples. · 071c69cd
  Jakob Stoklund Olesen authored Jan 13, 2012
  071c69cd
- Remove pointless mode line in .cpp file. · f35c8403
  Andrew Trick authored Jan 13, 2012
  f35c8403
- Try to clarify a little how exception handling works. · df9d7815
  Duncan Sands authored Jan 13, 2012
  df9d7815
- · 7066d280
  Devang Patel authored Jan 13, 2012
  7066d280
- Cosmetic patch for r148132. · 0a920fa2
  Stepan Dyatkovskiy authored Jan 13, 2012
  0a920fa2
- LoopUnswitch: All helper data that is collected during loop-unswitch... · cbcbdb23
  Stepan Dyatkovskiy authored Jan 13, 2012
  cbcbdb23
- Refactor. · 7ecdc6d4
  Devang Patel authored Jan 13, 2012
  7ecdc6d4
- Add new test. · 5d85276e
  Devang Patel authored Jan 13, 2012
  5d85276e
- Fixed comment. Thanks Duncan! · 97aafd5f
  Pete Cooper authored Jan 13, 2012
  97aafd5f
- Convert SHUFPD with the same register for both sources to PSHUFD if it would... · e52d86a7
  Craig Topper authored Jan 13, 2012
  e52d86a7
- use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1. · b1c2ebf6
  Craig Topper authored Jan 13, 2012
  b1c2ebf6
- Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones... · cb7e13d7
  Craig Topper authored Jan 13, 2012
  cb7e13d7
- test/CodeGen/ARM/test-sharedidx.ll: Fix for -Asserts. · 1b845f71
  NAKAMURA Takumi authored Jan 13, 2012
  1b845f71
- Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32. · 9f14d9f9
  Craig Topper authored Jan 13, 2012
  9f14d9f9
- Added the MachineSchedulerPass skeleton. · e77e84e4
  Andrew Trick authored Jan 13, 2012
  e77e84e4
- whitespace · d9accbf1
  Andrew Trick authored Jan 13, 2012
  d9accbf1