- Nov 14, 2012
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Andrew Trick authored
llvm-svn: 167917
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Craig Topper authored
llvm-svn: 167916
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Craig Topper authored
Set FFLOOR for vectors to expand on CellSPU to keep instruction selection from failing on llvm.floor of a vector. llvm-svn: 167914
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Craig Topper authored
llvm-svn: 167913
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Rafael Espindola authored
llvm-svn: 167912
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Sean Silva authored
llvm-svn: 167905
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Anton Korobeynikov authored
Do some cleanup of the code while here. Inspired by patch by Logan Chien! llvm-svn: 167904
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Sean Silva authored
llvm-svn: 167903
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Matt Beaumont-Gay authored
llvm-svn: 167894
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Michael J. Spencer authored
llvm-svn: 167893
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Nadav Rotem authored
llvm-svn: 167892
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Eric Christopher authored
temporarily as it is breaking the gdb bots. This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126. llvm-svn: 167886
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Jim Grosbach authored
llvm-svn: 167882
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- Nov 13, 2012
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Joe Abbey authored
Assignment of Bitcode ownership to Joe Abbey, after announcing proposal on LLVMdev and not hearing any major objections. Although it did spark a nice discussion regarding what it means to own something in LLVM. llvm-svn: 167881
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Andrew Trick authored
llvm-svn: 167880
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Andrew Trick authored
This option will eventually either be enabled unconditionally or replaced by a more general live range splitting optimization. llvm-svn: 167879
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Michael J. Spencer authored
llvm-svn: 167877
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NAKAMURA Takumi authored
Revert r167836, "llvm/test/Other/close-stderr.ll: Mark it as XFAIL:mingw32 for now.", corresponding to r167849. llvm-svn: 167876
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Ulrich Weigand authored
TLS symbols on PowerPC using the integrated assembler. llvm-svn: 167875
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Shankar Easwaran authored
llvm-svn: 167872
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Daniel Dunbar authored
llvm-svn: 167866
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Ulrich Weigand authored
generate them from PPCELFObjectWriter::getRelocTypeInner as appropriate. llvm-svn: 167864
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Ulrich Weigand authored
- lwaux - lhzux - stbu llvm-svn: 167863
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Ulrich Weigand authored
operand field name mismatches in: - AForm_3 (fmul, fmuls) - XFXForm_5 (mtcrf) - XFLForm (mtfsf) llvm-svn: 167862
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Ulrich Weigand authored
by using a new instruction format BForm_1. llvm-svn: 167861
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Ulrich Weigand authored
using a new instruction format AForm_4. llvm-svn: 167860
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Manman Ren authored
chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://12684358 llvm-svn: 167859
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Ulrich Weigand authored
physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. llvm-svn: 167855
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Shankar Easwaran authored
llvm-svn: 167853
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Shankar Easwaran authored
llvm-svn: 167852
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Andrew Trick authored
Working on reducing unit tests. This won't be enabled unless a subtarget enables misched. llvm-svn: 167851
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Chad Rosier authored
llvm-svn: 167849
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NAKAMURA Takumi authored
On MSYS, 70 is not seen, but 1. r127726 should be reworked. Candidate options are; 1) Use not exit(70), but _exit(70), in report_fatal_error(). 2) Return with _exit(70) in ~raw_ostream(). llvm-svn: 167836
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Duncan Sands authored
llvm-svn: 167830
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Duncan Sands authored
getelementptrs. llvm-svn: 167829
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Duncan Sands authored
Previously in a vector of pointers, the pointer couldn't be any pointer type, it had to be a pointer to an integer or floating point type. This is a hassle for dragonegg because the GCC vectorizer happily produces vectors of pointers where the pointer is a pointer to a struct or whatever. Vector getelementptr was restricted to just one index, but now that vectors of pointers can have any pointer type it is more natural to allow arbitrary vector getelementptrs. There is however the issue of struct GEPs, where if each lane chose different struct fields then from that point on each lane will be working down into unrelated types. This seems like too much pain for too little gain, so when you have a vector struct index all the elements are required to be the same. llvm-svn: 167828
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Benjamin Kramer authored
Part of a patch by Preston Briggs. llvm-svn: 167827
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Andrew Trick authored
This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. llvm-svn: 167826
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Andrew Trick authored
This adds the -join-globalcopies option which can be enabled by default once misched is also enabled. Ideally, the register coalescer would be able to split local live ranges in a way that produces copies that can be easily resolved by the scheduler. Until then, this heuristic should be good enough to at least allow the scheduler to run after coalescing. llvm-svn: 167825
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Alexey Samsonov authored
Figure out <size> argument of llvm.lifetime intrinsics at the moment they are created (during function inlining) llvm-svn: 167821
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