llvm-svn: 163601

llvm-svn: 163596

llvm-svn: 163594

llvm-svn: 163593

Add a pass that renames everything with metasyntatic names. This works well after using bugpoint to reduce the confusion presented by the original names, which no longer mean what they used to.

llvm-svn: 163592

Teach DAG combiner to constant fold FABS of a BUILD_VECTOR of ConstantFPs. Factor similar code out of FNEG DAG combiner.

llvm-svn: 163587

Patch by Brad Smith!

llvm-svn: 163584

The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.

For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.

llvm-svn: 163580

llvm-svn: 163579

right now. We'll fix PR13303 a different way.

llvm-svn: 163570

llvm-svn: 163569

llvm-svn: 163568

llvm-svn: 163567

llvm-svn: 163565

llvm-svn: 163561

llvm-svn: 163557

llvm-svn: 163556

test/CodeGen/X86/ms-inline-asm.ll: Relax for non-darwin x86 targets. '##InlineAsm' could not be seen in other hosts.

llvm-svn: 163554

and InlineAsmVariant don't match.

llvm-svn: 163550

llvm-svn: 163549

llvm-svn: 163547

llvm-svn: 163545

and update the printOperand() function accordingly.

llvm-svn: 163544

llvm-svn: 163542

llvm-svn: 163539

The ARM backend can eliminate cmp instructions by reusing flags from a
nearby sub instruction with similar arguments.

Don't do that if the sub is predicated - the flags are not written
unconditionally.

<rdar://problem/12263428>

llvm-svn: 163535

llvm-svn: 163532

llvm-svn: 163530

    
- Fix an remaining issue of PR11674 as well

llvm-svn: 163528

  Improve AQ instruction selection in the Hexagon MI scheduler.

llvm-svn: 163523

This folding happens as early as possible for performance reasons, and to make sure it isn't foiled by other transforms (e.g. forming FMAs).

llvm-svn: 163519

llvm-svn: 163518

- If a boolean value is generated from CMOV and tested as boolean value,
  simplify the use of test result by referencing the original condition.
  RDRAND intrinisc is one of such cases.

llvm-svn: 163516

Fix an assertion failure when optimising a shufflevector incorrectly into concat_vectors, and a followup bug with SelectionDAG::getNode() creating nodes with invalid types.

llvm-svn: 163511

llvm-svn: 163510

llvm-svn: 163509

Stack Coloring: When searching for disjoint regions, do not compare intervals twice or to theirself.

llvm-svn: 163508

llvm-svn: 163507

The VPSHUFB 256-bit instruction may be generated when one of input vector is undefined or zeroinitializer.
I've added the "zeroinitializer" case in this patch.

llvm-svn: 163506

llvm-svn: 163504