llvm-svn: 93591

Fix PR6019.  A load has more than one use if it feeds a bitconvert that
has more than one use.

llvm-svn: 93576

llvm-svn: 93567

llvm-svn: 93555

Improve llvm.dbg.declare intrinsic by referring directly to the storage in its first argument, via function-local metadata (instead of via a bitcast).
This patch also cleans up code that expects there to be a bitcast in the first argument and testcases that call llvm.dbg.declare.
It also strips old llvm.dbg.declare intrinsics that did not pass metadata as the first argument.

llvm-svn: 93531

llvm-svn: 93515

llvm-svn: 93511

Improve llvm.dbg.declare intrinsic by referring directly to the storage in its first argument, via function-local metadata (instead of via a bitcast).
This patch also cleans up code that expects there to be a bitcast in the first argument and testcases that call llvm.dbg.declare.

llvm-svn: 93504

llvm-svn: 93501

llvm-svn: 93494

llvm-svn: 93486

llvm-svn: 93468

llvm-svn: 93417

llvm-svn: 93410

llvm-svn: 93408

Now that LLParser, AsmWriter, BitcodeReader, and BitcodeWriter all correctly support function-local metadata, test it.

llvm-svn: 93406

added to the FSub version. However, the original version of this xform guarded
against doing this for floating point (!Op0->getType()->isFPOrFPVector()).

This is causing LLVM to perform incorrect xforms for code like:

void func(double *rhi, double *rlo, double xh, double xl, double yh, double yl){
  double mh, ml;
  double c = 134217729.0;
  double up, u1, u2, vp, v1, v2;
        
  up = xh*c;
  u1 = (xh - up) + up;
  u2 = xh - u1;
        
  vp = yh*c;
  v1 = (yh - vp) + vp;
  v2 = yh - v1;
        
  mh = xh*yh;
  ml = (((u1*v1 - mh) + (u1*v2)) + (u2*v1)) + (u2*v2);
  ml += xh*yl + xl*yh;
        
  *rhi = mh + ml;
  *rlo = (mh - (*rhi)) + ml;
}

The last line was optimized away, but rl is intended to be the difference
between the infinitely precise result of mh + ml and after it has been rounded
to double precision.

llvm-svn: 93369

llvm-svn: 93360

Commit some changes I had managed to lose last night while refactoring the code. Avoid change use of PHI instructions because it's not legal to insert any instructions before them.
This fixes PR6027.

llvm-svn: 93335

llvm-svn: 93313

different BlockAddress labels, but nothing semantically important.

Add a FIXME that BlockAddress codegen is broken if the LLVM BB has 
an empty name (e.g. strip was run).

llvm-svn: 93303

llvm-svn: 93286

flag doesn't exist there, and this is an x86 test.

llvm-svn: 93279

Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.

For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.

llvm-svn: 93278

in JT.

2) When cloning blocks for PHI or xor conditions, use
instsimplify to simplify the code as we go.  This allows us to 
squish common cases early in JT which opens up opportunities for
subsequent iterations, and allows it to completely simplify the
testcase.

llvm-svn: 93253

llvm-svn: 93244

on x86-64 linux with messages like this:
Error: Incorrect register `%r14' used with `l' suffix

llvm-svn: 93242

llvm-svn: 93230

llvm-svn: 93229

condition is a xor with a phi node.  This eliminates nonsense
like this from 176.gcc in several places:

 LBB166_84:
        testl   %eax, %eax
-       setne   %al
-       xorb    %cl, %al
-       notb    %al
-       testb   $1, %al
-       je      LBB166_85
+       je      LBB166_69
+       jmp     LBB166_85

This is rdar://7391699

llvm-svn: 93221

llvm-svn: 93206

Add manual ISD::OR fastisel selection routines. TableGen is no longer autogen them after 93152 and 93191.

llvm-svn: 93204

Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead.

llvm-svn: 93191

llvm-svn: 93189

Shorten up this testcase.

llvm-svn: 93187

llvm-svn: 93185

This fixes PR5980.

llvm-svn: 93184

has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.

FileCheckize, tidy, and extend a testcase to cover this case.

This fixes rdar://7527390.

llvm-svn: 93160

new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.

llvm-svn: 93158

llvm-svn: 93157