Commits · 6ee60bcf9b8048e7cdbf7caf99c5340e7e72091f · Roger Ferrer / llvm-epi · GitLab

Sep 17, 2016
- AMDGPU: Allow some control flow intrinsics to be CSEd · 6408c913
  Matt Arsenault authored Sep 16, 2016
  6408c913
Sep 16, 2016
- AMDGPU: Refactor kernel argument lowering · bbeb45af
  Tom Stellard authored Sep 16, 2016
  bbeb45af
- AMDGPU: Use SOPK compare instructions · 7ccf6cd1
  Matt Arsenault authored Sep 16, 2016
  7ccf6cd1
- AMDGPU/SI: Add support for triples with the mesa3d operating system · 0b76fc4c
  Tom Stellard authored Sep 16, 2016
  0b76fc4c
- [WebAssembly] Fix function types of CFGStackify tests · 3b04b7eb
  Derek Schuff authored Sep 16, 2016
  3b04b7eb
- [X86][SSE] Added vector sub combine tests · 99cc6f80
  Simon Pilgrim authored Sep 16, 2016
  99cc6f80
- [X86][SSE] Added vector add combine tests · 28568c47
  Simon Pilgrim authored Sep 16, 2016
  28568c47
- Make test slightly more explicit. NFC. · dadb71be
  Michael Kuperstein authored Sep 16, 2016
  dadb71be
- [AArch64][GlobalISel] Add default regbank mapping for int<>FP. · 85ef4a1c
  Ahmed Bougacha authored Sep 16, 2016
  85ef4a1c
- [AArch64][GlobalISel] Add default regbank mapping for G_FCMP. · 7b3b2e7f
  Ahmed Bougacha authored Sep 16, 2016
  7b3b2e7f
- [AArch64][GlobalISel] Add default regbank mapping for FP ops. · 90637f61
  Ahmed Bougacha authored Sep 16, 2016
  90637f61
- [AArch64][GlobalISel] Test default regbank mapping for G_ICMP. · 74db8faa
  Ahmed Bougacha authored Sep 16, 2016
  74db8faa
- [AArch64][GlobalISel] Add default regbank mappings for mixed-type ops. · 7306313e
  Ahmed Bougacha authored Sep 16, 2016
  7306313e
- [AArch64][GlobalISel] Add tests for default RegBank mappings. NFC. · 02629aae
  Ahmed Bougacha authored Sep 16, 2016
  02629aae
- Place the lowered phi instruction(s) before the DEBUG_VALUE entry · 830a8c1f
  Keith Walker authored Sep 16, 2016
  830a8c1f
- Reverting r281719, this is causing buildbot failures and timeouts again. · 22782534
  Sjoerd Meijer authored Sep 16, 2016
  22782534
- This is an attempt to reapply r280808: [ARM] Lower UDIV+UREM to UDIV+MLS · 23385c87
  Sjoerd Meijer authored Sep 16, 2016
  23385c87
- [ARM] Promote small global constants to constant pools · 0dc4708f
  James Molloy authored Sep 16, 2016
  0dc4708f
Sep 15, 2016
- [AArch64] Support for FP FMA when -ffp-contract=fast · 19b2aed3
  Evandro Menezes authored Sep 15, 2016
  19b2aed3
- Revert "[ARM] Promote small global constants to constant pools" · a0601a40
  Evgeniy Stepanov authored Sep 15, 2016
  a0601a40
- [ARM] Promote small global constants to constant pools · fe7fd879
  James Molloy authored Sep 15, 2016
  fe7fd879
- GlobalISel: legalize GEP instructions with small offsets. · 22d82cf1
  Tim Northover authored Sep 15, 2016
  22d82cf1
- GlobalISel: relax type constraints on G_ICMP to allow pointers. · 4cf0a482
  Tim Northover authored Sep 15, 2016
  4cf0a482
Sep 14, 2016
- [Stackmap] Added callsite counts to emitted function information. · 23f06e53
  Sanjoy Das authored Sep 14, 2016
  23f06e53
- [x86] regenerate checks · 3caf155b
  Sanjay Patel authored Sep 14, 2016
  3caf155b
- [x86] regenerate checks · c0899b96
  Sanjay Patel authored Sep 14, 2016
  c0899b96
- Revert "[ARM] Promote small global constants to constant pools" · e97d3b90
  Evgeniy Stepanov authored Sep 14, 2016
  e97d3b90
- [x86] regenerate checks · d56a27e2
  Sanjay Patel authored Sep 14, 2016
  d56a27e2
- Revert "AMDGPU: Use SOPK compare instructions" · f40b70fa
  Matt Arsenault authored Sep 14, 2016
  f40b70fa
- AMDGPU: Use SOPK compare instructions · f757c879
  Matt Arsenault authored Sep 14, 2016
  f757c879
- [X86][SSE] Improve recognition of i64 sitofp conversions that can be performed as i32 (PR29078) · a369219c
  Simon Pilgrim authored Sep 14, 2016
  a369219c
- AMDGPU: Support folding FrameIndex operands · 2bc198a3
  Matt Arsenault authored Sep 14, 2016
  2bc198a3
- AMDGPU: Improve splitting 64-bit bit ops by constants · fa5f767a
  Matt Arsenault authored Sep 14, 2016
  fa5f767a
- [ARM] Promote small global constants to constant pools · 13065b00
  James Molloy authored Sep 14, 2016
  13065b00
- [X86] Added i128 lshr+shl -> mask combine test · 67fdd15c
  Simon Pilgrim authored Sep 14, 2016
  67fdd15c
- Fix code-gen crash on Power9 for insert_vector_elt with variable index (PR30189) · d5deb489
  Nemanja Ivanovic authored Sep 14, 2016
  d5deb489
- [X86][SSE] Don't blend vector shifts with MOVSS/MOVSD directly, lower from generic shuffle · ba325e3a
  Simon Pilgrim authored Sep 14, 2016
  ba325e3a
- Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently" · 9790d8f8
  James Molloy authored Sep 14, 2016
  9790d8f8
- GlobalISel: mark pointer stores as legal on AArch64. · 1c7825fd
  Tim Northover authored Sep 14, 2016
  1c7825fd
- This reapplies r281304. The issue was that I had missed · 724023a1
  Sjoerd Meijer authored Sep 14, 2016
  724023a1