When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.

rdar://12700702

llvm-svn: 167937

llvm-svn: 167936

llvm-svn: 167933

llvm-svn: 167928

llvm-svn: 167926

This seems like redundant leftovers from r142288 - exposing
TargetData::parseSpecifier to LLParser - which got reverted. Removes
redunant td != NULL checks in parseSpecifier, and simplifies the
interface to parseSpecifier and init.

llvm-svn: 167924

llvm-svn: 167922

llvm-svn: 167921

llvm-svn: 167917

llvm-svn: 167916

Set FFLOOR for vectors to expand on CellSPU to keep instruction selection from failing on llvm.floor of a vector.

llvm-svn: 167914

llvm-svn: 167913

llvm-svn: 167912

llvm-svn: 167905

Do some cleanup of the code while here.

Inspired by patch by Logan Chien!

llvm-svn: 167904

llvm-svn: 167903

llvm-svn: 167894

llvm-svn: 167893

llvm-svn: 167892

temporarily as it is breaking the gdb bots.

This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126.

llvm-svn: 167886

llvm-svn: 167882

Assignment of Bitcode ownership to Joe Abbey, after announcing proposal on
LLVMdev and not hearing any major objections.  Although it did spark a nice 
discussion regarding what it means to own something in LLVM.

llvm-svn: 167881

llvm-svn: 167880

This option will eventually either be enabled unconditionally or
replaced by a more general live range splitting optimization.

llvm-svn: 167879

llvm-svn: 167877

Revert r167836, "llvm/test/Other/close-stderr.ll: Mark it as XFAIL:mingw32 for now.", corresponding to r167849.

llvm-svn: 167876

TLS symbols on PowerPC using the integrated assembler.

llvm-svn: 167875

llvm-svn: 167872

llvm-svn: 167866

generate them from PPCELFObjectWriter::getRelocTypeInner
as appropriate.

llvm-svn: 167864

 - lwaux
 - lhzux
 - stbu

llvm-svn: 167863

operand field name mismatches in:
 - AForm_3  (fmul, fmuls)
 - XFXForm_5 (mtcrf)
 - XFLForm (mtfsf)

llvm-svn: 167862

by using a new instruction format BForm_1.

llvm-svn: 167861

using a new instruction format AForm_4.

llvm-svn: 167860

chain is correctly setup.

As an example, if the original load must happen before later stores, we need
to make sure the constructed VZEXT_LOAD is constrained to be before the stores.

rdar://12684358

llvm-svn: 167859

physical register as candidate for common subexpression elimination
in MachineCSE.

This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc
caused by MachineCSE invalidly merging two separate DYNALLOC insns.

llvm-svn: 167855

llvm-svn: 167853

llvm-svn: 167852

Working on reducing unit tests.
This won't be enabled unless a subtarget enables misched.

llvm-svn: 167851

llvm-svn: 167849