Commits · 730f3c857472dd33eda184c8124da148d9de52ef · Roger Ferrer / llvm-epi · GitLab

Aug 22, 2013
- SelectionDAG: Make sure stores are always added to the LegalizedNodes list · 1b2c2d84
  Tom Stellard authored Aug 21, 2013
  1b2c2d84
Aug 17, 2013
- R600: Expand vector FRINT ops · b249b757
  Tom Stellard authored Aug 16, 2013
  b249b757
- R600: Expand vector FFLOOR ops · ad3aff24
  Tom Stellard authored Aug 16, 2013
  ad3aff24
- R600: Expand vector float operations for both SI and R600 · a92ff879
  Tom Stellard authored Aug 16, 2013
  a92ff879
Aug 16, 2013
- R600/SI: Add pattern for xor of i1 · 8522270d
  Michel Danzer authored Aug 16, 2013
  8522270d
- R600/SI: Fix broken encoding of DS_WRITE_B32 · 20680b1c
  Michel Danzer authored Aug 16, 2013
  20680b1c
- Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions" · dba25713
  Tom Stellard authored Aug 16, 2013
  dba25713
- R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions · 82bef57f
  Tom Stellard authored Aug 16, 2013
  82bef57f
- R600: Add support for global vector loads with element types less than 32-bits · b03edeca
  Tom Stellard authored Aug 16, 2013
  b03edeca
- R600: Add support for global vector stores with elements less than 32-bits · fbab827e
  Tom Stellard authored Aug 16, 2013
  fbab827e
- R600: Add support for i16 and i8 global stores · d3ee8c10
  Tom Stellard authored Aug 16, 2013
  d3ee8c10
- R600: Add support for v4i32 stores on Cayman · 6d1379e1
  Tom Stellard authored Aug 16, 2013
  6d1379e1
- R600: Enable folding of inline literals into REQ_SEQUENCE instructions · 16da74c2
  Tom Stellard authored Aug 16, 2013
  16da74c2
- R600: Change the RAT instruction assembly names so they match the docs · ac00f9df
  Tom Stellard authored Aug 16, 2013
  ac00f9df
- [tests] Cleanup initialization of test suffixes. · 9efbedfd
  Daniel Dunbar authored Aug 16, 2013
  9efbedfd
Aug 15, 2013
- R600/SI: Improve legalization of vector operations · d86003e3
  Tom Stellard authored Aug 14, 2013
  d86003e3
- R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics · 6785065a
  Tom Stellard authored Aug 14, 2013
  6785065a
- R600/SI: Convert v16i8 resource descriptors to i128 · 9fa1791a
  Tom Stellard authored Aug 14, 2013
  9fa1791a
- R600/SI: Use i8 types for resource descriptors in tests · b81df0c7
  Tom Stellard authored Aug 14, 2013
  b81df0c7
- R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2 · 8e5da413
  Tom Stellard authored Aug 14, 2013
  8e5da413
- R600/SI: Assign a register class to the $vaddr operand for MIMG instructions · 16a9a205
  Tom Stellard authored Aug 14, 2013
  16a9a205
- R600/SI: Handle MSAA texture targets · 3494b7ee
  Tom Stellard authored Aug 14, 2013
  3494b7ee
- R600/SI: Allow conversion between v32i8 and v8i32 · 20ee94f1
  Tom Stellard authored Aug 14, 2013
  20ee94f1
- R600/SI: Add pattern for fp_to_uint · 73c31d54
  Tom Stellard authored Aug 14, 2013
  73c31d54
Aug 13, 2013
- R600: Set scheduling preference to Sched::Source · fc455471
  Tom Stellard authored Aug 12, 2013
  fc455471
Aug 10, 2013
- R600/SI: FMA is faster than fmul and fadd for f64 · d3a039fe
  Niels Ole Salscheider authored Aug 10, 2013
  d3a039fe
- R600/SI: Add FMA pattern · 6509ac65
  Niels Ole Salscheider authored Aug 10, 2013
  6509ac65
Aug 08, 2013
- R600/SI: Implement fp32<->fp64 conversions · 719fbc9a
  Niels Ole Salscheider authored Aug 08, 2013
  719fbc9a
- R600/SI: Implement sint<->fp64 conversions · 4715d886
  Niels Ole Salscheider authored Aug 08, 2013
  4715d886
Aug 07, 2013
- R600/SI: Use VSrc_* register classes as the default classes for types · 2f7cdda5
  Tom Stellard authored Aug 06, 2013
  2f7cdda5
- R600/SI: Add more special cases for opcodes to ensureSRegLimit() · 4c0ffccb
  Tom Stellard authored Aug 06, 2013
  4c0ffccb
Aug 06, 2013
- Factor FlattenCFG out from SimplifyCFG · aa664d9b
  Tom Stellard authored Aug 06, 2013
  aa664d9b
- R600/SI: Add missing test for r187749 · eef2ad92
  Tom Stellard authored Aug 05, 2013
  eef2ad92
Aug 01, 2013
- R600: Add 64-bit float load/store support · 0344cdfe
  Tom Stellard authored Aug 01, 2013
  0344cdfe
- R600: Use 64-bit alignment for 64-bit kernel arguments · 53698938
  Tom Stellard authored Aug 01, 2013
  53698938
- R600/SI: Custom lower i64 ZERO_EXTEND · 98f675a9
  Tom Stellard authored Aug 01, 2013
  98f675a9
Jul 31, 2013
- Revert "R600: Non vector only instruction can be scheduled on trans unit" · ca69a53b
  Tom Stellard authored Jul 31, 2013
  ca69a53b
- R600: Avoid more than 4 literals in the same instruction group at scheduling · bb3f9311
  Vincent Lejeune authored Jul 31, 2013
  bb3f9311
- R600: Non vector only instruction can be scheduled on trans unit · df18804e
  Vincent Lejeune authored Jul 31, 2013
  df18804e
Jul 30, 2013
- R600/SI: Expand vector fp <-> int conversions · aa313d0a
  Tom Stellard authored Jul 30, 2013
  aa313d0a