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  1. Dec 18, 2014
  2. Dec 17, 2014
    • Toma Tabacu's avatar
      [mips] Set GCC-compatible MIPS asssembler options before inline asm blocks. · a23f13c3
      Toma Tabacu authored
      Summary:
      When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives,
      while GCC uses the default options if an assembly-level function contains inline assembly code.
      
      This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example).
      
      This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end.
      
      Reviewers: dsanders
      
      Reviewed By: dsanders
      
      Subscribers: llvm-commits
      
      Differential Revision: http://reviews.llvm.org/D6637
      
      llvm-svn: 224425
      a23f13c3
  3. Apr 11, 2013
  4. Apr 10, 2013
    • Jack Carter's avatar
      Mips specific inline asm operand modifier 'D' · b04e357d
      Jack Carter authored
      Modifier 'D' is to use the second word of a double integer.
      
      We had previously implemented the pure register varient of 
      the modifier and this patch implements the memory reference.
      
      
      
      #include "stdio.h"
      
      int b[8] = {0,1,2,3,4,5,6,7};
      void main()
      {
          int i;
          
          // The first word. Notice, no 'D'
          {asm (
          "lw    %0,%1;"
          : "=r" (i)
          : "m" (*(b+4))
          );}
          
          printf("%d\n",i);
      
          // The second word
          {asm (
          "lw    %0,%D1;"
          : "=r" (i)
          : "m" (*(b+4))
          );}
          
          printf("%d\n",i);
      }
      
      llvm-svn: 179135
      b04e357d
  5. May 12, 2012
  6. Oct 24, 2011
  7. Sep 10, 2011
    • Akira Hatanaka's avatar
      Fix test cases. · 56247076
      Akira Hatanaka authored
      Generate code for Mips32r1 unless a Mips32r2 feature is tested.
      
      llvm-svn: 139433
      56247076
  8. Jun 21, 2011
  9. Jun 09, 2011
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