Commits · 86b6b394114145b2b47b55fbff934ad1bfbdef4e · Roger Ferrer / llvm-epi · GitLab

Aug 31, 2022
- [llvm][test] precommit test for D130127 · 86b6b394
  Nick Desaulniers authored Aug 31, 2022
  86b6b394
- [test][InstCombine] Precommit some undef/noundef tests · 8c7b1030
  Arthur Eubanks authored Aug 31, 2022
  
  8c7b1030
- [AArch64][CostModel][NFC] Specify target datalayout explicitly for cost analysis test. · 75f1b328
  Mingming Liu authored Aug 29, 2022
  75f1b328
- [Symbolizer] Handle {{{bt}}} symbolizer markup element. · ea992255
  Daniel Thornburgh authored Aug 05, 2022
  ea992255
- [CostModel][X86] Add and/or/xor general cost kinds support · ad8e4dd2
  Simon Pilgrim authored Aug 31, 2022
  ad8e4dd2
- [SLP] Add FMA test case with missing or partial fast-math flags. · e68594ca
  Florian Hahn authored Aug 31, 2022
  e68594ca
- [DAG] extractShiftForRotate - replace assertion for shift opcode with an early-out · eaede4b5
  Simon Pilgrim authored Aug 31, 2022
  eaede4b5
- [LV] Add test case where SCEV is needed to remove vector backedge. · faad5675
  Florian Hahn authored Aug 31, 2022
  faad5675
- [AArch64 - SVE]: Use SVE to lower reduce.fadd. · a6d9c944
  Hassnaa Hamdi authored Aug 24, 2022
  a6d9c944
- [LV] Fix test cases where vector loop never executed. · 1ed555a6
  Florian Hahn authored Aug 31, 2022
  1ed555a6
- [LLParser] Add test for phi first class type error (NFC) · 9f6c09de
  Nikita Popov authored Aug 31, 2022
  
  9f6c09de
- [LLParser] Allow zero-input phi nodes · 5921bc42
  Nikita Popov authored Aug 31, 2022
  5921bc42
- [llvm-readobj][COFF] Print load config GuardFlags as enum flags · 94baaa6a
  Alvin Wong authored Aug 31, 2022
  94baaa6a
- [AArch64-SVE-fixed]: · d8655bde
  Hassnaa Hamdi authored Aug 31, 2022
  d8655bde
- [DAG] visitFreeze - account for operand depth when calling... · 9d228002
  Simon Pilgrim authored Aug 31, 2022
  9d228002
- [ARM] Add a phase ordering test for MVE intrinsic remainder vectorization/unrolling. NFC · 225faddf
  David Green authored Aug 31, 2022
  
  225faddf
- [InstCombine] Use getInsertionPointAfterDef() in freeze fold · ad66bc42
  Nikita Popov authored Jul 13, 2022
  ad66bc42
- [Reassociate] Use getInsertionPointerAfterDef() · 8f3fd26b
  Nikita Popov authored Jul 13, 2022
  8f3fd26b
- [GVN] Add another test for phi translation miscompile (NFC) · b10e508c
  Nikita Popov authored Aug 31, 2022
  
  b10e508c
- [LoongArch] Support floating-point number reciprocal · fb9d6763
  gonglingqin authored Aug 31, 2022
  fb9d6763
- [DirectX backend] change MinVectorRegisterBitWidth to 32. · 6917799e
  Xiang Li authored Aug 28, 2022
  6917799e
- [RISCV] Add cost model for select and integer compare instructions. · 45c1ce32
  Jianjian GUAN authored Aug 20, 2022
  45c1ce32
- [RISCV][test] Add cost model coverage for compare instructions. · 4fd53fd8
  Jianjian GUAN authored Aug 29, 2022
  4fd53fd8
- [InstCombine] add support for multi-use Y of (X op Y) op Z --> (Y op Z) op X · 35a3048c
  Chenbing Zheng authored Aug 31, 2022
  35a3048c
- [AtomicExpand] Make floating point conversion happens before fence insertion · ad2f7fd2
  Kai Luo authored Aug 31, 2022
  ad2f7fd2
- [GlobalISel] Explicitly fail trying to translate `gc.statepoint` and related intrinsics · 2fdf963d
  Markus Böck authored Aug 31, 2022
  2fdf963d
Aug 30, 2022
- [NFC] Move a test case across files. · 4df696fb
  Mingming Liu authored Aug 19, 2022
  4df696fb
- [SLP]Fix PR57447: Assertion `!getTreeEntry(V) && "Scalar already in tree!"' failed. · ec06df94
  Alexey Bataev authored Aug 30, 2022
  ec06df94
- [RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros. · 893f5e95
  Craig Topper authored Aug 30, 2022
  893f5e95
- [AMDGPU] Limit TID / wavefrontsize uniformness to 1D kernels · fd1f8c85
  Stanislav Mekhanoshin authored Aug 29, 2022
  fd1f8c85
- [AMDGPU] Precommit two tests showing missed combines to v_med3 · f9433161
  Justin Bogner authored Aug 30, 2022
  
  f9433161
- [InstCombine] add tests for xor-of-ctlz/cttz; NFC · 16e96a7e
  Sanjay Patel authored Aug 30, 2022
  
  16e96a7e
- [InstCombine] add tests for signbit test using lshr; NFC · 67cbd25d
  Sanjay Patel authored Aug 29, 2022
  
  67cbd25d
- [SVE] Fix SVEDup0 matching -0.0f · 40999cbd
  Stephen Long authored Aug 30, 2022
  40999cbd
- [NFC][AArch64] Specify datalayout explicitly for cast.ll and · 3785234b
  Mingming Liu authored Aug 29, 2022
  3785234b
- [BasicBlockUtils] Amend test for loop metadata. · 3d5ea539
  Hendrik Greving authored May 24, 2022
  3d5ea539
- [CostModel][X86] Account for add/sub 512-bit vector splitting costs on non-AVX512BW targets · 78304450
  Simon Pilgrim authored Aug 30, 2022
  
  78304450
- [NFC][LoopLoadElim] Extending type-mismatch testing · 92c41727
  Jolanta Jensen authored Aug 19, 2022
  92c41727
- [llvm-size] Fix missing file name for darwin output format with non-Mach-O · 25fdcb8e
  Shivam Gupta authored Aug 30, 2022
  25fdcb8e
- [llvm-otool] Print dyld_info output before chained_fixup output · b9d63e10
  Nico Weber authored Aug 29, 2022
  b9d63e10