Commits · 93699f4d58744e7a3d74ed8c00ffec4c64c0abb9 · Roger Ferrer / llvm-epi · GitLab

Nov 29, 2017
- [ARM GlobalISel] Fix selecting G_BRCOND · 863b5b05
  Diana Picus authored Nov 29, 2017
  863b5b05
- [X86][AVX512] Setup unary (PABS/VPLZCNT/VPOPCNT/VPCONFLICT/VMOV*DUP) instruction scheduler classes · 756348c1
  Simon Pilgrim authored Nov 29, 2017
  756348c1
- [AMDGPU][MC][GFX9] Corrected mapping of GFX9 v_add/sub/subrev_u32 · 1ac7177a
  Dmitry Preobrazhensky authored Nov 29, 2017
  1ac7177a
- [X86][SSE] Merged sse2_unpack and sse2_unpack PUNPCK instruction templates. NFCI. · e3291de2
  Simon Pilgrim authored Nov 29, 2017
  e3291de2
- [X86][SSE] Merged sse2_pack and sse2_pack_y PACKSS/PACKUS instruction templates. NFCI. · da957722
  Simon Pilgrim authored Nov 29, 2017
  da957722
- [ARM] Add support for armv7e-m to the .arch directive · 9ea2eaeb
  Oliver Stannard authored Nov 29, 2017
  9ea2eaeb
- [X86] Remove setOperationAction Promote for ISD::SINT_TO_FP MVT::v8i16/v16i8/v16i16. · e3515001
  Craig Topper authored Nov 29, 2017
  e3515001
- [PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended. · aab3ef76
  Sean Fertile authored Nov 29, 2017
  aab3ef76
- DAG: Add nuw when splitting loads and stores · b655fa9c
  Matt Arsenault authored Nov 29, 2017
  b655fa9c
- AMDGPU: Select DS insts without m0 initialization · 3f71c0e3
  Matt Arsenault authored Nov 29, 2017
  3f71c0e3
- [X86] Promote fp_to_sint v16f32->v16i16/v16i8 to avoid scalarization. · fbf7b3bf
  Craig Topper authored Nov 29, 2017
  fbf7b3bf
- [X86] Mark ISD::FP_TO_UINT v16i8/v16i16 as Promote under AVX512 instead of... · 88ffb5d4
  Craig Topper authored Nov 28, 2017
  88ffb5d4
- AMDGPU: Enable IPRA · 607a7566
  Matt Arsenault authored Nov 28, 2017
  607a7566
- [X86] Tag CLFLUSHOPT with same scheduling behaviour as CLFLUSH · b9aa93cb
  Simon Pilgrim authored Nov 28, 2017
  b9aa93cb
- [X86][SSE] Add SSE_SHUFP OpndItins · f490c6ef
  Simon Pilgrim authored Nov 28, 2017
  f490c6ef
Nov 28, 2017
- [X86][SSE] Add SSE_UNPCK/SSE_PUNPCK OpndItins · 8f623947
  Simon Pilgrim authored Nov 28, 2017
  8f623947
- [X86][SSE] Use SSE_PACK OpndItins in PACKSS/PACKUS instruction definitions · 1bc7b0e1
  Simon Pilgrim authored Nov 28, 2017
  1bc7b0e1
- Fix VS2017 narrowing conversion warning. NFCI · 14d3fd29
  Simon Pilgrim authored Nov 28, 2017
  14d3fd29
- [X86] Remove unused variable. · ab9bfc90
  Craig Topper authored Nov 28, 2017
  ab9bfc90
- [X86] Remove code from combineUIntToFP that tried to favor UINT_TO_FP if legal... · a27f1e67
  Craig Topper authored Nov 28, 2017
  a27f1e67
- [X86] Remove custom lowering for uint_to_fp from vXi8/vXi16. · 3aaa71f2
  Craig Topper authored Nov 28, 2017
  3aaa71f2
- [Hexagon] Use stable sort for HexagonShuffler to remove non-deterministic ordering · e0173664
  Mandeep Singh Grang authored Nov 28, 2017
  e0173664
- [PowerPC] Allow tail calls of fastcc functions from C CallingConv functions. · e200016e
  Sean Fertile authored Nov 28, 2017
  e200016e
- [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal · 7fe7acc6
  Daniel Sanders authored Nov 28, 2017
  7fe7acc6
- [X86][SSE] Add SSE_HADDSUB/SSE_PABS/SSE_PALIGN OpndItins · d49bd0cd
  Simon Pilgrim authored Nov 28, 2017
  d49bd0cd
- [X86] In lowerVectorShuffleAsElementInsertion, if were able to find a scalar... · dd429562
  Craig Topper authored Nov 28, 2017
  dd429562
- [Hexagon] Make sure to zero-extend bytes before building a vector · 081e458e
  Krzysztof Parzyszek authored Nov 28, 2017
  081e458e
- [X86][X87] Tag FP_TO_INT_IN_MEM pseudos with hasNoSchedulingInfo · 4fecbd88
  Simon Pilgrim authored Nov 28, 2017
  4fecbd88
- AMDGPU: Add num spilled s/vgprs to metadata · 06ae4ec7
  Konstantin Zhuravlyov authored Nov 28, 2017
  06ae4ec7
- [CodeGen] Print register names in lowercase in both MIR and debug output · 9d7bb0cb
  Francis Visoiu Mistrih authored Nov 28, 2017
  9d7bb0cb
- [WebAssembly] Support bitcasted function addresses with varargs. · 2803bfaf
  Dan Gohman authored Nov 28, 2017
  2803bfaf
- [X86][X87] Tag FTST x87 instruction scheduler class · ece5bc35
  Simon Pilgrim authored Nov 28, 2017
  ece5bc35
- [X86][X87] Tag FABS/FCHS/FSQRT/FSIN/FCOS x87 instruction scheduler classes · 0747a7e8
  Simon Pilgrim authored Nov 28, 2017
  0747a7e8
- Use getStoreSize() in various places instead of 'BitSize >> 3'. · f0ff20f1
  Jonas Paulsson authored Nov 28, 2017
  f0ff20f1
- [CodeGen] Rename functions PrintReg* to printReg* · 9d419d3b
  Francis Visoiu Mistrih authored Nov 28, 2017
  9d419d3b
- [X86][3DNow] Add instruction itinerary and scheduling classes for femms/prefetch/prefetchw · 8dc603b0
  Simon Pilgrim authored Nov 28, 2017
  8dc603b0
- AMDGPU: Re-organize the outer loop of SILoadStoreOptimizer · b4f28ded
  Nicolai Haehnle authored Nov 28, 2017
  b4f28ded
- AMDGPU: Consistently check for immediates in SIInstrInfo::FoldImmediate · 39980dac
  Nicolai Haehnle authored Nov 28, 2017
  39980dac
- [WebAssembly] Handle errors better in fast-isel. · 3ff73cfb
  Dan Gohman authored Nov 28, 2017
  3ff73cfb
- [X86] Remove some unused pattern fragments from td file. NFC · 640a3c1e
  Craig Topper authored Nov 28, 2017
  640a3c1e