Commits · 95291a0e34c74d9be0ad216465a2a2e9db9610d4 · Roger Ferrer / llvm-epi · GitLab

Feb 24, 2020
- Reland "[ms] [llvm-ml] Improve data support, adding names and complex initializers." · 95291a0e
  Eric Astor authored Feb 24, 2020
  95291a0e
- [MachineVerifier] Doing ::calcRegsPassed in RPO: ~35% faster MV, NFC · 6f87b162
  Roman Tereshin authored Feb 23, 2020
  6f87b162
- [Hexagon] Lower bitcast of a vector predicate · a8a4f99a
  Ikhlas Ajbar authored Jan 09, 2020
  a8a4f99a
- Revert "[ms] [llvm-ml] Improve data support, adding names and complex initializers." · 9fe769a9
  Eric Astor authored Feb 24, 2020
  9fe769a9
- [ms] [llvm-ml] Improve data support, adding names and complex initializers. · c2e272f8
  Eric Astor authored Feb 24, 2020
  c2e272f8
- [X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation · 72732843
  Craig Topper authored Feb 24, 2020
  72732843
- [AMDGPU] use llvm_unreachable instead of default for rp set · 4135077e
  Stanislav Mekhanoshin authored Feb 23, 2020
  4135077e
- [LLVM-C] Add bindings for addCoroutinePassesToExtensionPoints · 2a7a989c
  Ayke van Laethem authored Feb 24, 2020
  2a7a989c
- [SelectionDAG] Merge constant SDNode arithmetic into foldConstantArithmetic · 53b597cf
  Simon Pilgrim authored Feb 24, 2020
  53b597cf
- [MachO] Add cpu(sub)type tests and improve error handling · 7b0a5683
  Francis Visoiu Mistrih authored Feb 24, 2020
  7b0a5683
- [AVR] Disassemble register operands · 5b2046c9
  Ayke van Laethem authored Feb 05, 2020
  5b2046c9
- [X86] combineX86ShuffleChain - select X86ISD::FAND/ISD::AND based on MaskVT · daac8dba
  Simon Pilgrim authored Feb 24, 2020
  daac8dba
- [AVR] Don't assert on an undefined operand · d1af6011
  Ayke van Laethem authored Feb 04, 2020
  d1af6011
- [AVR] Use correct register class for mul instructions · a5424ded
  Ayke van Laethem authored Feb 24, 2020
  a5424ded
- [XCOFF][AIX] Fix incorrect alignment for function descriptor csect · bee70bff
  jasonliu authored Feb 24, 2020
  bee70bff
- [NFC] Fix typo in error message · 400b6c08
  serge-sans-paille authored Feb 24, 2020
  
  400b6c08
- [X86] getTargetShuffleInputs - check that the source inputs are all the right size. · 59d8d13c
  Simon Pilgrim authored Feb 24, 2020
  59d8d13c
- [PowerPC][AIX] Spill/restore the callee-saved condition register bits. · 8efc2f57
  Sean Fertile authored Feb 24, 2020
  8efc2f57
- [CostModel][X86] We don't need a scale factor for SLM extract costs · b8243887
  Simon Pilgrim authored Feb 24, 2020
  b8243887
- [MIR][ARM] MachineOperand comments · 7efabe5c
  Sjoerd Meijer authored Feb 24, 2020
  7efabe5c
- [AArch64][SVE] Add the SVE dupq_lane intrinsic · f87f23c8
  Kerry McLaughlin authored Feb 24, 2020
  f87f23c8
- [RDA][ARM][LowOverheadLoops] Iteration count IT blocks · a67eb221
  Sam Parker authored Feb 24, 2020
  a67eb221
- [ORC] Remove spammy debug print · 8c893cac
  Benjamin Kramer authored Feb 24, 2020
  
  8c893cac
- [AArch64][SVE] Add intrinsics for SVE2 cryptographic instructions · f2ff1534
  Kerry McLaughlin authored Feb 24, 2020
  f2ff1534
- [Intrinsic] Add fixed point saturating division intrinsics. · 6e561d1c
  Bevin Hansson authored Dec 16, 2019
  6e561d1c
- [profile] Don't dump counters when forking and don't reset when calling exec** functions · 8f46269f
  Calixte Denizet authored Feb 10, 2020
  8f46269f
- [MC] Widen the functional unit type from 32 to 64 bits. · c3f36acc
  Bevin Hansson authored Dec 09, 2019
  c3f36acc
- [ARM][MVE] Combine more extending masked loads · 03756a41
  Sam Parker authored Feb 21, 2020
  03756a41
- [JITLink] Add a MachO x86-64 GOT and Stub bypass optimization. · 27a79b72
  Lang Hames authored Feb 23, 2020
  27a79b72
- [X86] When creating X86ISD::MGATHER nodes from AVX2 gather intrinsics, cast... · 7a7146cf
  Craig Topper authored Feb 23, 2020
  7a7146cf
- [X86] Use custom isel for gather/scatter instructions. · f1b8ec33
  Craig Topper authored Feb 23, 2020
  f1b8ec33
- [SelectionDAG] Remove ISD::LIFETIME_START/LIFETIME_END from assert in getMemIntrinsicNode. · 3a6bb32b
  Craig Topper authored Feb 23, 2020
  3a6bb32b
- [NFC][PowerPC] Refactor the tryAndWithMask() · 8b3a62dc
  QingShan Zhang authored Feb 24, 2020
  8b3a62dc
- IR printing for single function with the new pass manager. · bae33a7c
  Hongtao Yu authored Feb 23, 2020
  bae33a7c
- [X86] Remove most X86 specific subclasses of MemSDNode. Just use a... · 5a705186
  Craig Topper authored Feb 23, 2020
  5a705186
- [X86] Enable the use of movlps for i64 atomic load on 32-bit targets with sse1. · 15b6aa74
  Craig Topper authored Feb 23, 2020
  15b6aa74
- [X86] Use FIST for i64 atomic stores on 32-bit targets without SSE. · 2a10f801
  Craig Topper authored Feb 23, 2020
  
  2a10f801
Feb 23, 2020
- [SystemZ] Support the kernel back chain. · 82879c29
  Jonas Paulsson authored Feb 19, 2020
  82879c29
- Recommit "[PatternMatch] Match XOR variant of unsigned-add overflow check." · 7769030b
  Florian Hahn authored Feb 23, 2020
  7769030b
- [SDAG] fold fsub -0.0, undef to undef rather than NaN · a253a2a7
  Sanjay Patel authored Feb 23, 2020
  a253a2a7