Quite a major error here: the expansions for the Pseudos with and without
folded load were mixed up. Fortunately it only affects ARM-mode, when not using
movw/movt, on Darwin. I'm guessing no-one actually uses that combination.

llvm-svn: 223986

DW_OP_const <const> doesn't describe a constant value, but a value at a constant address.
The proper way to describe a constant value is DW_OP_constu <const>, DW_OP_stack_value.

Added DW_OP_stack_value to the stack.

-This line, and those below, will be ignored--

M    lib/CodeGen/AsmPrinter/DwarfDebug.cpp
A    test/DebugInfo/incorrect-variable-debugloc1.ll

llvm-svn: 223981

llvm-svn: 223978

Fix PR21694. r219517 added a use of SCEV divide in HowFarToZero computation.  This divide can produce incorrect results as we are using an unsigned divide for what should be a modular divide.  This change reverts back to a more conservative computation using trailing zeros.

llvm-svn: 223974

llvm-svn: 223971

No functional change intended.

llvm-svn: 223970

Zero is usually a nicer constant to have than -1.

llvm-svn: 223969

X shifted by undef results in undef because the undef value can
represent values greater than the width of the operands.

llvm-svn: 223968

llvm-svn: 223967

These methods are only used by MCJIT and are very specific to it. In fact, they
are also fairly specific to the fact that we have a dynamic linker of
relocatable objects.

llvm-svn: 223964

In the large code model we have to first get the address of the GOT entry, load
the address of the constant, and then load the constant itself.

To avoid these loads and the GOT entry alltogether this commit changes the way
how FP constants are materialized in the large code model. The constats are now
materialized in a GPR and then bitconverted/moved into the FPR.

Reviewed by Tim Northover

Fixes rdar://problem/16572564.

llvm-svn: 223941

llvm-svn: 223940

llvm-svn: 223933

Pass looks for equivalent functions that are mergable and folds them.

llvm-svn: 223931

Add patterns to match SSE (shufpd) and AVX (vpermilpd) shuffle codegen
when storing the high element of a v2f64. The existing patterns were
only checking for an unpckh type of shuffle. 

http://llvm.org/bugs/show_bug.cgi?id=21791

Differential Revision: http://reviews.llvm.org/D6586

llvm-svn: 223929

llvm-svn: 223926

Dividing by zero yields an undefined value.

llvm-svn: 223924

Exact shifts always keep the non-zero bits of their input.  This means
it keeps it's undef bits.

llvm-svn: 223923

EltsFromConsecutiveLoads was apparently only ever called for 128-bit vectors, and assumed this implicitly. r223518 started calling it for AVX-sized vectors, causing the code path that had this assumption to crash.
This adds a check to make this path fire only for 128-bit vectors.

Differential Revision: http://reviews.llvm.org/D6579

llvm-svn: 223922

We already optimized rem %X, 0 to undef, we should do the same for div.

llvm-svn: 223919

llvm-svn: 223918

Summary:
This patch gives me just enough to leverage the existing functionality in `TestRunner` for use in `libc++` and `libc++abi` .

It does the following:
* Adds the `UNSUPPORTED` tag to `TestRunner.parseIntegratedTestScript`.
* Allows `parseIntegratedTestScript` to return an empty script if a script is not required by the caller.



Reviewers: ddunbar, EricWF

Reviewed By: EricWF

Subscribers: cfe-commits, llvm-commits

Differential Revision: http://reviews.llvm.org/D6589

llvm-svn: 223915

llvm-svn: 223911

Since Value objects can't have null bytes in their name, we shouldn't
allow them in the labels of basic blocks.

llvm-svn: 223907

Don't call `dropAllReferences()` from `MDNode::~MDNode()`, call it
directly from `~MDNodeFwdDecl()` and `~GenericMDNode()`.

llvm-svn: 223904

llvm-svn: 223903

llvm-svn: 223899

As indicated by the tests, it is possible to feed the AsmParser an
invalid datalayout string.  We should verify the result of parsing this
string regardless of whether or not we have assertions enabled.

llvm-svn: 223898

We can't mark partially undefined registers, so we have to allow reading
a register in the machine verifier if just parts of a register are
defined.

llvm-svn: 223896

In the subregister liveness tracking case we do not create implicit
reads on partial register writes anymore, still we need to produce a new
SSA value for partial writes so the live segment has to end.

llvm-svn: 223895

llvm-svn: 223894

This iterator iterates over subregister and their associated subregister indices
at the same time.

llvm-svn: 223893

Adding the implicit defs/uses to the superregisters is semantically questionable
but was not dangerous before as the register allocator never assigned the same
register to two overlapping LiveIntervals even when the actually live
subregisters do not overlap. With subregister liveness tracking enabled this
does actually happen and leads to subsequent bugs if we don't stop adding
the superregister defs/uses.

llvm-svn: 223892

llvm-svn: 223891

This allows it to add subregister ranges into the union.

llvm-svn: 223890

Now we can relate lanemasks in a virtual register to register units.

llvm-svn: 223889

llvm-svn: 223888

llvm-svn: 223887

llvm-svn: 223886

llvm-svn: 223885