llvm-svn: 169085

Fixes PR14465.

Differential Revision: http://llvm-reviews.chandlerc.com/D148

llvm-svn: 169084

llvm-svn: 169083

Also check in a case to repeat the issue, on which 'opt -globalopt' consumes 1.6GB memory.
The big memory footprint cause is that current GlobalOpt one by one hoists and stores the leaf element constant into the global array, in each iteration, it recreates the global array initializer constant and leave the old initializer alone. This may result in many obsolete constants left.
For example:  we have global array @rom = global [16 x i32] zeroinitializer
After the first element value is hoisted and installed:   @rom = global [16 x i32] [ 1, 0, 0, ... ]
After the second element value is installed:  @rom = global [16 x 32] [ 1, 2, 0, 0, ... ]        // here the previous initializer is obsolete
...
When the transform is done, we have 15 obsolete initializers left useless.

llvm-svn: 169079

2012-11-30-misched-dbg.ll had crashed. Then (MDNode)N was "!{}".
I am not sure it would be ill-formed or not.

llvm-svn: 169074

 - Each macro instantiation introduces a new buffer, and FindBufferForLoc() is
   linear, so previously macro instantiation could be N^2 for some pathological
   inputs.

llvm-svn: 169073

Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker").
rdar://12790302.

llvm-svn: 169072

Assertion failed: (VNI && "No value to read by operand")
rdar://12790267.

llvm-svn: 169071

Assertion failed: (itr != mi2iMap.end() && "Instruction not found in maps.")
rdar://12777252.

llvm-svn: 169070

assert (RemainingInstrs == 0 && "Instruction count mismatch!")

rdar://12776937.

llvm-svn: 169069

The TwoAddressInstructionPass takes the machine code out of SSA form by
expanding REG_SEQUENCE instructions into copies. It is no longer
necessary to rewrite the registers used by a REG_SEQUENCE instruction
because the new coalescer algorithm can do it now.

REG_SEQUENCE is just converted to a sequence of sub-register copies now.

llvm-svn: 169067

llvm-svn: 169064

part of the compile unit CU and start separating out information into
the various sections that will be pulled out later.

WIP.

llvm-svn: 169061

MachineCopyPropagation doesn't understand super-register liveness well
enough to be able to remove implicit defs of super-registers.

This fixes a problem in ARM/2012-01-26-CopyPropKills.ll that is exposed
by an future TwoAddressInstructionPass change. The KILL instructions are
removed before the machine code is emitted.

llvm-svn: 169060

llvm-svn: 169056

llvm-svn: 169055

llvm-svn: 169053

llvm-svn: 169052

llvm-svn: 169050

reversed the logic of the log2 detection routine to reduce the number of nested ifs

llvm-svn: 169049

llvm-svn: 169048

uses. APFloat::convert() takes the pointer to the fltSemantics
variable, which is later accessed it in ~APFloat() desctructor.
That is, semantics must still be alive at the moment we delete
APFloat.

Found by experimental AddressSanitizer use-after-scope checker.

llvm-svn: 169047

llvm-svn: 169046

The original patch removed a bunch of code that the SjLjEHPrepare pass placed
into the entry block if all of the landing pads were removed during the
CodeGenPrepare class. The more natural way of doing things is to run the CGP
*before* we run the SjLjEHPrepare pass.

Make it so!

llvm-svn: 169044

llvm-svn: 169043

This causes llc to repeat the module compilation N times, making it
possible to get more accurate information from -time-passes when
compiling small modules.

llvm-svn: 169040

This avoids unidentified duplicates in the pass execution time report
when a pass runs more than once in the pass manager pipeline.

llvm-svn: 169039

llvm-svn: 169038

llvm-svn: 169026

reviewed by Michael Ilseman <milseman@apple.com>

llvm-svn: 169025

Codegen was failing with an assertion because of unexpected vector
operands when legalizing the selection DAG for a MUL instruction.

The asserting code was legalizing multiplies for vectors of size 128
bits. It uses a custom lowering to try and detect cases where it can
use a VMULL instruction instead of a VMOVL + VMUL.  The code was
looking for input operands to the MUL that had been sign or zero
extended. If it found the extended operands it would drop the
sign/zero extension and use the original vector size as input to a
VMULL instruction.

The code assumed that the original input vector was 64 bits so that
after dropping the extension it would fit directly into a D register
and could be used as an operand of a VMULL instruction. The input
code that trigger the failure used a vector of <4 x i8> that was
sign extended to <4 x i32>. It was not safe to drop the sign
extension in this case because the original vector is only 32 bits
wide. The fix is to insert a sign extension for the vector to reach
the required 64 bit size. In this particular example, the vector would
need to be sign extented to a <4 x i16>.

llvm-svn: 169024

llvm-svn: 169020

llvm-svn: 169018

Remove the use of LPPassManager. We can remove LPM because we dont need to run any additional loop passes on the new vector loop.

llvm-svn: 169016

llvm-svn: 169002

instead of 1 or true (?!)

llvm-svn: 169001

FIXME: Please add another RUN line if you would like to check also on ppc64.
llvm-svn: 168999

instruction (vmaddfp) to conform with IEEE to ensure the sign of a zero
result when resulting product is -0.0.

The -0.0 vector addend to vmaddfp is generated by a creating a vector
with full bits sets and then shifting each elements by 31-bits to the
left, resulting in a vector of 0x80000000 (or -0.0 as float).

The 'buildvec_canonicalize.ll' was adjusted to reflect this change and
the 'vec_mul.ll' was complemented with the float vector multiplication
test.

llvm-svn: 168998

llvm-svn: 168997

Rationale:
1) This was the name in the comment block. ;]
2) It matches Clang's __has_feature naming convention.
3) It matches other compiler-feature-test conventions.

Sorry for the noise. =]

I've also switch the comment block to use a \brief tag and not duplicate
the name.

llvm-svn: 168996