pointers or not depending upon the function attributes.

llvm-svn: 181180

X86ISelLowering has support to treat:
(icmp ne (and (xor %flags, -1), (shl 1, flag)), 0)

as if it were actually:
(icmp eq (and %flags, (shl 1, flag)), 0)

However, r179386 has code at the InstCombine level to handle this.

llvm-svn: 181145

This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.

llvm-svn: 180935

llvm-svn: 180910

As DejaGNU is deprecated, it seems pipe-jam issue doesn't exist any more.

llvm-svn: 180892

llvm-svn: 180889

Patch by Joshua Magee.

llvm-svn: 180842

llvm-svn: 180838

llvm-svn: 180837

because it breaks some buildbots.

This reverts commit 180816.

llvm-svn: 180819

register-indirect address with an offset of 0.
It used to be that a DBG_VALUE is a register-indirect value if the offset
(operand 1) is nonzero. The new convention is that a DBG_VALUE is
register-indirect if the first operand is a register and the second
operand is an immediate. For plain registers use the combination reg, reg.

rdar://problem/13658587

llvm-svn: 180816

This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.

llvm-svn: 180796

llvm-svn: 180776

llvm-svn: 180754

llvm-svn: 180744

- Revise previous patches of the same purpose by fixing
  *) grep <PA> | not grep <PB> semantically is not the same as
     CHECK: <PA>{{^<PB>.*$}} as the former will check all occurrences of <PA>
     while the later only check the first match. As the result, CHECK needs
     putting in all place where <PA> occurs.
  *) grep <PA> | count <N> needs a final CHECK-NOT of the same pattern.
     (As 'CHECK-<N>' is proposed for discussion, converting 'grep | count <N>'
      where N > 1 is postponed.)

llvm-svn: 180742

Hopefully brings the windows buildbots back to life.

llvm-svn: 180630

llvm-svn: 180600

This already helps SSE2 x86 a lot because it lacks an efficient way to
represent a vector select. The long term goal is to enable the backend to match
a canonicalized pattern into a single instruction (e.g. vabs or pabs).

llvm-svn: 180597

latency for certain models of the Intel Atom family, by converting
instructions into their equivalent LEA instructions, when it is both
useful and possible to do so.

llvm-svn: 180573

assembly is requesting a 64-bit register, which is invalid for i386.
rdar://13731657

llvm-svn: 180445

llvm-svn: 180092

llvm-svn: 180003

This reverts commit r179840 with a fix to test/DebugInfo/two-cus-from-same-file.ll

I'm not sure why that test only failed on ARM & MIPS and not X86 Linux, even
though the debug info was clearly invalid on all of them, but this ought to fix
it.

llvm-svn: 179996

llvm-svn: 179970

llvm-svn: 179954

llvm-svn: 179937

Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter).

llvm-svn: 179925

Allow tail call opportunity detection through nested and/or multiple iterations of extractelement/insertelement indirection

llvm-svn: 179924

Based on the patch by David Nadlinger!

llvm-svn: 179889

llvm-svn: 179888

Add a testcase to make sure we generate the proper compact unwind section for a function that cannot produce a compact unwind encoding.

llvm-svn: 179887

This reverts commit r179836 as it seems to have caused test failures.

llvm-svn: 179840

Adding another CU-wide list, in this case of imported_modules (since they
should be relatively rare, it seemed better to add a list where each element
had a "context" value, rather than add a (usually empty) list to every scope).
This takes care of DW_TAG_imported_module, but to fully address PR14606 we'll
need to expand this to cover DW_TAG_imported_declaration too.

llvm-svn: 179836

This pattern started popping up in vectorized min/max reductions.

llvm-svn: 179797

In X86FastISel::X86SelectStore(), improperly aligned stores are rejected and
handled by the DAG-based ISel.  However, X86FastISel::X86SelectLoad() makes
no such requirement.  There doesn't appear to be an x86 architectural
correctness issue with allowing potentially unaligned store instructions.
This patch removes this restriction.

Patch by Jim Stichnot.

llvm-svn: 179774

for the sdiv/srem/udiv/urem bitcode instructions.  This is done for the i8,
i16, and i32 types, as well as i64 for the x86_64 target.

Patch by Jim Stichnoth

llvm-svn: 179715

llvm-svn: 179532

The order of copies depends on queue order, which is not very stable.

llvm-svn: 179456

llvm-svn: 179455