Commits · b1d0762eda22a3fe4a52a321b2b8a81ebc353da4 · Roger Ferrer / llvm-epi · GitLab

Dec 09, 2020
- Set VF range lower bound to 1 when smallest type can't be determined · 333d7d74
  Vineet Kumar authored Nov 23, 2020
  
  333d7d74
- Add builtins for nontemporal loads and stores · e99f1b98
  Roger Ferrer authored Dec 09, 2020
  
  e99f1b98
- Make these passes aware of the nontemporal bit · 034a7f8a
  Roger Ferrer authored Dec 09, 2020
  034a7f8a
Dec 04, 2020
- Add nontemporal bit to vtype · 70539adb
  Roger Ferrer authored Dec 04, 2020
  
  70539adb
Dec 02, 2020
- Refactor so we do not drift that much with what we do in EPI-0.7 · e373437d
  Roger Ferrer authored Dec 02, 2020
  e373437d
Dec 01, 2020
- Fold broadcasts for binary widenings and narrowings · 06aa3023
  Roger Ferrer authored Dec 01, 2020
  
  06aa3023
Nov 30, 2020
- [RISCV] Remove unused Addend parameter from classifySymbolRef. NFC · e6db1416
  Fangrui Song authored Nov 29, 2020
  e6db1416
Nov 29, 2020
- [RISCV] Change predicate on InstAliases for GORCI/GREVI/SHFLI/UNSHFLI to... · 84aad9b5
  Craig Topper authored Nov 29, 2020
  84aad9b5
Nov 28, 2020
- [RISCV] Add tests for existing (rotr (bswap X), (i32 16))->grevi pattern for... · 6ee22ca6
  Craig Topper authored Nov 27, 2020
  6ee22ca6
Nov 27, 2020
- [RISCV] Replace getSimpleValueType() with getValueType() in DAG combines to... · 8709d9d8
  Craig Topper authored Nov 27, 2020
  8709d9d8
- [RISCV] Replace sexti32/zexti32 in isel patterns where only one part of their... · f325b4bb
  Craig Topper authored Nov 27, 2020
  f325b4bb
- [RISCV] Don't remove (and X, 0xffffffff) from inputs when matching... · e0481048
  Craig Topper authored Nov 26, 2020
  e0481048
- [RISCV] Add isel patterns to use SBSET for (1 << X) by using X0 as the input. · 5836e520
  Craig Topper authored Nov 26, 2020
  
  5836e520
Nov 26, 2020
- [RISCV] Add isel patterns for sbsetw/sbclrw/sbinvw with sext_inreg as the root. · d9500c2e
  Craig Topper authored Nov 26, 2020
  d9500c2e
- [RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32. · 2254e014
  Craig Topper authored Nov 25, 2020
  
  2254e014
- [RISCV] Remove unused PatFrag argument from the tablegen class used for c.beqz/c.bnez. NFC · f78ad68b
  Craig Topper authored Nov 25, 2020
  
  f78ad68b
- [RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd · ed95cafb
  Craig Topper authored Nov 25, 2020
  ed95cafb
Nov 25, 2020
- [RISCV] Make SMIN/SMAX/UMIN/UMAX legal with Zbb extension. · 751b0d97
  Craig Topper authored Nov 25, 2020
  751b0d97
- [RISCV] Custom type legalize i32 fshl/fshr on RV64 with Zbt. · c26e8697
  Craig Topper authored Nov 25, 2020
  c26e8697
Nov 24, 2020
- [RISCV] Add GHC calling convention · a8dc2110
  Luís Marques authored Nov 24, 2020
  a8dc2110
- Revert "[RISCV] Add GHC calling convention" · e4d93802
  Luís Marques authored Nov 24, 2020
  e4d93802
- [RISCV] Add GHC calling convention · f8317bb2
  Luís Marques authored Nov 24, 2020
  f8317bb2
- [RISCV] Combine GREVI sequences · ca1f2f27
  Fraser Cormack authored Nov 20, 2020
  ca1f2f27
Nov 23, 2020
- [RISCV] Remove unused VM register class · 03dab46d
  Craig Topper authored Nov 23, 2020
  03dab46d
- [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma... · 4252f777
  Craig Topper authored Nov 23, 2020
  4252f777
Nov 22, 2020
- [RISCV] Use separate Lo and Hi MemOperands when expanding BuildPairF64Pseudo and SplitF64Pseudo. · 84b82227
  Craig Topper authored Nov 22, 2020
  84b82227
Nov 20, 2020
- [RISCV] Put RV32 before RV64 in the ValueTypeByHwMode and RegInfoByHwMode... · 9211da42
  Craig Topper authored Nov 20, 2020
  9211da42
- [RISCV] Remove RV32 HwMode. Use DefaultMode for RV32 · 77e25b5b
  Craig Topper authored Nov 20, 2020
  77e25b5b
- [RISCV] Custom type legalize i32 bswap/bitreverse to GREVIW on RV64 with Zbp extension · 6a1d8b91
  Craig Topper authored Nov 20, 2020
  6a1d8b91
- [RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb. · 78767b7f
  Craig Topper authored Nov 20, 2020
  78767b7f
Nov 19, 2020
- [RISCV] Lower GREVI and GORCI as custom nodes · 1ac9b548
  Fraser Cormack authored Nov 11, 2020
  1ac9b548
- [RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot · 6b0fc1f3
  Craig Topper authored Nov 18, 2020
  6b0fc1f3
Nov 18, 2020
- [RISCV] Use register class VR for V instruction operands directly. · 44cd03ad
  Hsiangkai Wang authored Nov 18, 2020
  44cd03ad
- Fix {sign,zero} extend in vector register · e74647d4
  Roger Ferrer authored Nov 17, 2020 and Roger Ferrer committed Nov 18, 2020
  e74647d4
Nov 17, 2020
- [AsmWriter] Factor out mnemonic generation to accessible getMnemonic. · b2f4c5fd
  Florian Hahn authored Nov 17, 2020
  b2f4c5fd
Nov 16, 2020
- [RISCV] When matching SROIW, check all 64 bits of the OR mask · 124c93c5
  Craig Topper authored Nov 16, 2020
  124c93c5
- [RISCV] Use a macro to simplify getTargetNodeName · fe9dc2e5
  Fraser Cormack authored Nov 13, 2020
  fe9dc2e5
Nov 13, 2020
- llvmbuildectomy - replace llvm-build by plain cmake · 9218ff50
  serge-sans-paille authored Oct 09, 2020
  9218ff50
Nov 12, 2020
- [RISCV] Don't include CodeGen layer files in MC layer · 0add5f91
  Craig Topper authored Nov 12, 2020
  0add5f91
- [RISCV] Add an ANDI to shift amount of FSL/FSR instructions · 9ca02d6f
  Craig Topper authored Nov 12, 2020
  9ca02d6f