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  1. Aug 04, 2010
  2. Aug 02, 2010
  3. Jul 31, 2010
  4. Jul 30, 2010
    • Benjamin Kramer's avatar
      Tweak suppressions. · f9d5fe7f
      Benjamin Kramer authored
      llvm-svn: 109858
      f9d5fe7f
    • Jim Grosbach's avatar
      Many Thumb2 instructions can reference the full ARM register set (i.e., · d343166a
      Jim Grosbach authored
      have 4 bits per register in the operand encoding), but have undefined
      behavior when the operand value is 13 or 15 (SP and PC, respectively).
      The trivial coalescer in linear scan sometimes will merge a copy from
      SP into a subsequent instruction which uses the copy, and if that
      instruction cannot legally reference SP, we get bad code such as:
        mls r0,r9,r0,sp
      instead of:
        mov r2, sp
        mls r0, r9, r0, r2
      
      This patch adds a new register class for use by Thumb2 that excludes
      the problematic registers (SP and PC) and is used instead of GPR
      for those operands which cannot legally reference PC or SP. The
      trivial coalescer explicitly requires that the register class
      of the destination for the COPY instruction contain the source
      register for the COPY to be considered for coalescing. This prevents
      errant instructions like that above.
      
      PR7499
      
      llvm-svn: 109842
      d343166a
    • Benjamin Kramer's avatar
      Supress valgrind errors from python. · 2e357b62
      Benjamin Kramer authored
      llvm-svn: 109818
      2e357b62
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  18. Jul 09, 2010
    • Bruno Cardoso Lopes's avatar
      Start the support for AVX instructions with 256-bit %ymm registers. A couple of · 792e906b
      Bruno Cardoso Lopes authored
      notes:
      - The instructions are being added with dummy placeholder patterns using some 256
        specifiers, this is not meant to work now, but since there are some multiclasses
        generic enough to accept them,  when we go for codegen, the stuff will be already
        there.
      - Add VEX encoding bits to support YMM
      - Add MOVUPS and MOVAPS in the first round
      - Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
      - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
        file.
      
      llvm-svn: 107996
      792e906b
    • Bob Wilson's avatar
      --- Reverse-merging r107947 into '.': · 6586e9b2
      Bob Wilson authored
      U    utils/TableGen/FastISelEmitter.cpp
      --- Reverse-merging r107943 into '.':
      U    test/CodeGen/X86/fast-isel.ll
      U    test/CodeGen/X86/fast-isel-loads.ll
      U    include/llvm/Target/TargetLowering.h
      U    include/llvm/Support/PassNameParser.h
      U    include/llvm/CodeGen/FunctionLoweringInfo.h
      U    include/llvm/CodeGen/CallingConvLower.h
      U    include/llvm/CodeGen/FastISel.h
      U    include/llvm/CodeGen/SelectionDAGISel.h
      U    lib/CodeGen/LLVMTargetMachine.cpp
      U    lib/CodeGen/CallingConvLower.cpp
      U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
      U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
      U    lib/CodeGen/SelectionDAG/FastISel.cpp
      U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
      U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
      U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
      U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
      U    lib/Target/XCore/XCoreISelLowering.cpp
      U    lib/Target/XCore/XCoreISelLowering.h
      U    lib/Target/X86/X86ISelLowering.cpp
      U    lib/Target/X86/X86FastISel.cpp
      U    lib/Target/X86/X86ISelLowering.h
      
      llvm-svn: 107987
      6586e9b2
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