llvm-svn: 75017

llvm-svn: 75016

llvm-svn: 75015

llvm-svn: 75012

llvm-svn: 75011

Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.

llvm-svn: 75010

and cases alphabetically.  No functionality change.

llvm-svn: 75001

llvm-svn: 75000

Fixed build, requires std header before using std::string

llvm-svn: 74995

Mark sublw_cc and subfw_cc as Terminator insns so that they are part of the terminator insns for a basic block alongwith branch insns. This way a copy is not getting inserted between cmp and branch during PHIElimination disturbing the status flags.

llvm-svn: 74992

these instructions, no autoupgrade or backwards compatibility support is
provided.

llvm-svn: 74991

Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.

llvm-svn: 74988

llvm-svn: 74985

llvm-svn: 74982

llvm-svn: 74981

llvm-svn: 74980

functionality change.

llvm-svn: 74979

VSETCC must define all bits, which is different than it was documented
to before.  Since all targets that implement VSETCC already have this
behavior, and we don't optimize based on this, just change the 
documentation.  We now get nice code for vec_compare.ll

llvm-svn: 74978

llvm-svn: 74977

llvm-svn: 74976

llvm-svn: 74974

llvm-svn: 74973

Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan.

llvm-svn: 74972

U    lib/Target/X86/X86RegisterInfo.cpp
U    lib/Target/X86/X86RegisterInfo.h

Temporarily revert. This was causing an infinite loop in the linker on Leopard.

llvm-svn: 74970

for now, conservatively return false.

llvm-svn: 74969

patch, instead of one I didn't.

llvm-svn: 74968

as "X" constraint and "P" modifier on x86.  Make this work.
(Change may not be sufficient to fix it for non-Darwin, but
I'm pretty sure it won't break anything.)
gcc.apple/asm-block-32.c
gcc.apple/asm-block-33.c

llvm-svn: 74967

the input is legal (4 x i32)

llvm-svn: 74964

llvm-svn: 74963

llvm-svn: 74962

finishes off enough support for vector compares to get the icmp/fcmp
version of 2008-07-23-VSetCC.ll passing.

llvm-svn: 74961

(vector of bool).

llvm-svn: 74960

eliminate the former.

llvm-svn: 74959

instead of having a separate intrinsic for each value.

llvm-svn: 74958

llvm-svn: 74957

srcdir!=objdir.

llvm-svn: 74956

llvm-svn: 74955

vfcmp version.  We actually get better code for this silly testcase.

llvm-svn: 74954

llvm-svn: 74953

prologue like this:

__Z3fooi:
Leh_func_begin1:
LBB1_0: ## entry
        pushl   %ebp
Llabel1:
        movl    %esp, %ebp
Llabel2:
        pushl   %esi
Llabel3:
        subl    $20, %esp
        call    "L1$pb"
"L1$pb":
        popl    %esi

The "pushl %ebp" needs a table entry specifying the offset. The "movl %esp,
%ebp" makes %ebp the new stack frame register, so that needs to be specified in
DWARF. And "pushl %esi" saves the callee-saved %esi register, which also needs
to be specified in DWARF.

Before, all of this logic was in one method. This didn't work too well, because
as you can see there are multiple FDE line entries that need to be created.

This fix creates the "MachineMove" objects directly when they're needed; instead
of waiting until the end, and losing information.

llvm-svn: 74952