Commits · b9d298ecf23ed9dcc0daa8a32e2b7d894aee1f98 · Roger Ferrer / llvm-epi · GitLab

Apr 06, 2018
- [X86] Remove InstRWs for basic arithmetic instructions from Sandy Bridge scheduler model. · b9d298ec
  Craig Topper authored Apr 06, 2018
  b9d298ec
- [X86] Attempt to model basic arithmetic instructions in the... · f0d04261
  Craig Topper authored Apr 06, 2018
  f0d04261
- [X86] Add an extra store address cycle to WriteRMW in the Sandy... · f131b600
  Craig Topper authored Apr 06, 2018
  f131b600
- [X86] Merge itineraries for CLC, CMC, and STC. · 22d25a08
  Craig Topper authored Apr 06, 2018
  22d25a08
- [X86][SandyBridge] Add (V)DPPS memory fold latencies · 09eeb3a8
  Simon Pilgrim authored Apr 06, 2018
  09eeb3a8
- [X86][SandyBridge] SBWriteResPair +5cy Memory Folds · 8a83f16c
  Simon Pilgrim authored Apr 06, 2018
  8a83f16c
- [X86][SkylakeServer] Merge 2 InstRW entries to the same sched group. NFCI. · fd1f4fe5
  Simon Pilgrim authored Apr 06, 2018
  fd1f4fe5
Apr 05, 2018
- [X86] Separate CDQ and CDQE in the scheduler model. · fbe3132f
  Craig Topper authored Apr 05, 2018
  fbe3132f
- [X86] Add MOVZPQILo2PQIrr to the Sandy Bridge scheduler model · 4cc38277
  Craig Topper authored Apr 05, 2018
  4cc38277
- [X86] Add LEAVE instruction to the scheduler models using the same data as... · 3b0b96c5
  Craig Topper authored Apr 05, 2018
  3b0b96c5
- [X86] Remove some InstRWs for plain store instructions on Sandy Bridge. · c6bb36a3
  Craig Topper authored Apr 05, 2018
  c6bb36a3
- [X86] Synchronize the SchedRW on some EVEX instructions with their VEX equivalents. · 9eec2025
  Craig Topper authored Apr 05, 2018
  9eec2025
- [X86] Disassembler support for having an ADSIZE prefix affect instructions... · 665f7441
  Craig Topper authored Apr 05, 2018
  665f7441
- [X86] Use WriteFShuffle256 for VEXTRACTF128 to be consistent with VEXTRACTI128... · 6ecdb03f
  Craig Topper authored Apr 05, 2018
  6ecdb03f
- [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. · c74ad502
  Andrea Di Biagio authored Apr 05, 2018
  c74ad502
- [X86] Revert r329251-329254 · 15303dda
  Craig Topper authored Apr 05, 2018
  15303dda
- [X86] Synchronize the SchedRW on some EVEX instructions with their VEX equivalents. · 25c7110a
  Craig Topper authored Apr 05, 2018
  25c7110a
- [X86] Use WriteFShuffle256 for VEXTRACTF128 to be consistent with VEXTRACTI128... · 4b1fdd49
  Craig Topper authored Apr 05, 2018
  4b1fdd49
- [X86] Auto-generate complete checks. NFC · 5c365574
  Craig Topper authored Apr 05, 2018
  5c365574
Apr 04, 2018
- [MachineOutliner] Add `useMachineOutliner` target hook · bccd18b8
  Jessica Paquette authored Apr 04, 2018
  bccd18b8
- [X86] Separate BSWAP32r and BSWAP64r scheduling data in... · 498875fa
  Craig Topper authored Apr 04, 2018
  498875fa
- Sort targetgen calls in lib/Target/*/CMakeLists. · 1cbd0969
  Nico Weber authored Apr 04, 2018
  1cbd0969
- Make helpers static. NFC. · 1fc0da48
  Benjamin Kramer authored Apr 04, 2018
  1fc0da48
- [X86] Use the same predicate for the load for PMOVSXBQ and PMOVZXBQ. · a30db995
  Craig Topper authored Apr 04, 2018
  a30db995
- [X86] Use loadi16/loadi32 predicates in multiply patterns · a3cac956
  Craig Topper authored Apr 04, 2018
  a3cac956
- [X86] Remove more dead code left over from the handling of i8/i16... · 88e38e3e
  Craig Topper authored Apr 04, 2018
  88e38e3e
- [X86] Remove dead code for handling i8/i16 UMUL_LOHI/SMUL_LOHI from X86ISelDAGToDAG.cpp. NFC · afa22edc
  Craig Topper authored Apr 04, 2018
  afa22edc
- [X86] Remove some code that was only needed when i1 was a legal type. NFC · 3064c15d
  Craig Topper authored Apr 04, 2018
  3064c15d
- Fix bad #include path in r329139 · b3247331
  Vlad Tsyrklevich authored Apr 04, 2018
  b3247331
- Add the ShadowCallStack pass · e3446017
  Vlad Tsyrklevich authored Apr 04, 2018
  e3446017
- [MachineOutliner] Test for X86FI->getUsesRedZone() as well as Attribute::NoRedZone · 5fa2a637
  Jessica Paquette authored Apr 03, 2018
  5fa2a637
Apr 03, 2018
- [MC][Tablegen] Allow the definition of processor register files in the... · 9da4d6db
  Andrea Di Biagio authored Apr 03, 2018
  9da4d6db
- [X86] Reduce number of OpPrefix bits in TSFlags to 2. NFCI · 9b6a65b9
  Craig Topper authored Apr 03, 2018
  9b6a65b9
Apr 02, 2018
- [X86] Reduce Store Forward Block issues in HW - Recommit after fixing Bug 36346 · 92746830
  Lama Saba authored Apr 02, 2018
  92746830
- [X86][Silvermont] Use correct latency and throughput information for divide... · 96729cd6
  Craig Topper authored Apr 02, 2018
  96729cd6
- [X86][SkylakeServer] Correct throughput for 512-bit sqrt and divide. · 6a814904
  Craig Topper authored Apr 02, 2018
  6a814904
- [X86] Correct the throughput for divide instructions in Sandy... · 8104f266
  Craig Topper authored Apr 02, 2018
  8104f266
- [X86] Fix the SchedRW for AVX512 shift instructions. · dc740943
  Craig Topper authored Apr 02, 2018
  dc740943
- [X86] Give the AVX512 VEXTRACT instructions the same SchedRWs as the SSE/AVX versions. · 5fb1dc2d
  Craig Topper authored Apr 02, 2018
  5fb1dc2d
- [X86] Add an itinerary to BTR64rr. · caec723a
  Craig Topper authored Apr 02, 2018
  caec723a