Commits · c1bd968c8c102d7af01adf95d7af39e4a98f0d9e · Roger Ferrer / llvm-epi · GitLab

Dec 13, 2017
- [X86] Add POP/PUSH schedule tests · c1bd968c
  Simon Pilgrim authored Dec 13, 2017
  c1bd968c
- Simplify. NFC. · 13dbf944
  Rafael Espindola authored Dec 13, 2017
  13dbf944
- [OPENMP] Support `reduction` clause on target-based directives. · 3f96fe6d
  Alexey Bataev authored Dec 13, 2017
  3f96fe6d
- [Function] Remove trailing end-of-line whitespace. NFC. · dde93259
  Brian M. Rzycki authored Dec 13, 2017
  dde93259
- [sanitizer] Introduce a vDSO aware timing function · f50246da
  Kostya Kortchinsky authored Dec 13, 2017
  f50246da
- [AArch64] fix an issue with older /proc/cpuinfo layout · 7634f709
  Paul Osmialowski authored Dec 13, 2017
  7634f709
- [scudo] Inline getScudoChunk function. · 4ac0b1e6
  Kostya Kortchinsky authored Dec 13, 2017
  4ac0b1e6
- [clangd] Fix bool conversion operator of UniqueFunction · 3db40ffe
  Ilya Biryukov authored Dec 13, 2017
  3db40ffe
- [OPENMP] Fix handling of clauses in clause parsing mode. · 3f82cfc3
  Alexey Bataev authored Dec 13, 2017
  3f82cfc3
- Fix link failure on one build bot introduced by r320584. · 6af75240
  Nemanja Ivanovic authored Dec 13, 2017
  6af75240
- Reverted r320229. It broke tests on builder llvm-clang-x86_64-expensive-checks-win. · 9dee3f0a
  Galina Kistanova authored Dec 13, 2017
  9dee3f0a
- [X86] Add PREFETCH schedule tests · 0bd31a83
  Simon Pilgrim authored Dec 13, 2017
  0bd31a83
- [X86] Add XCHG schedule tests · 1df18ee3
  Simon Pilgrim authored Dec 13, 2017
  1df18ee3
- [X86] Add MOVNTI schedule tests · 9d9f1701
  Simon Pilgrim authored Dec 13, 2017
  9d9f1701
- [PowerPC] MachineSSA pass to reduce the number of CR-logical operations · 6f590bf8
  Nemanja Ivanovic authored Dec 13, 2017
  6f590bf8
- [X86] Add ENTER/LEAVE schedule tests · 88e6f83f
  Simon Pilgrim authored Dec 13, 2017
  88e6f83f
- [X86] Add IMUL schedule tests · cef5b64f
  Simon Pilgrim authored Dec 13, 2017
  cef5b64f
- [X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule tests · f00ea1b4
  Simon Pilgrim authored Dec 13, 2017
  f00ea1b4
- [X86] Add ARPL/BOUND schedule tests · 46ec195d
  Simon Pilgrim authored Dec 13, 2017
  46ec195d
- [Hexagon] Add front-end support for Hexagon V65 · cc5cd2c0
  Krzysztof Parzyszek authored Dec 13, 2017
  cc5cd2c0
- [clangd] Try to workaround MSVC compilation failure. · a1d324d8
  Ilya Biryukov authored Dec 13, 2017
  a1d324d8
- [clangd] clang-format the source code. NFC · 5a85b8e6
  Ilya Biryukov authored Dec 13, 2017
  5a85b8e6
- [clangd] Implemented logging using Context · 940901e8
  Ilya Biryukov authored Dec 13, 2017
  940901e8
- [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools · 845e5dce
  Alex Bradbury authored Dec 13, 2017
  845e5dce
- [clangd] Remove the const specifier of the takeSymbol method · acc90d17
  Haojian Wu authored Dec 13, 2017
  acc90d17
- [FuzzMutate] Only generate loads and stores to the first class sized types · d209ff98
  Igor Laevsky authored Dec 13, 2017
  d209ff98
- [FuzzMutate] Avoid zero sized aggregates · f39a2926
  Igor Laevsky authored Dec 13, 2017
  f39a2926
- [FuzzMutate] Correctly split landingpad blocks · 541f9707
  Igor Laevsky authored Dec 13, 2017
  541f9707
- [X86][SSE] MOVMSK only uses the sign bit from each vector element · f51f4d36
  Simon Pilgrim authored Dec 13, 2017
  f51f4d36
- [RISCV] Implement floating point assembler pseudo instructions · fa7e4ec8
  Alex Bradbury authored Dec 13, 2017
  fa7e4ec8
- Reintroduce r320049, r320014 and r319894. · e0edb664
  Igor Laevsky authored Dec 13, 2017
  e0edb664
- [DAG] Promote ADDCARRY / SUBCARRY · e8d4e88b
  Roger Ferrer Ibanez authored Dec 13, 2017
  e8d4e88b
- [CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug output · b41dbbe3
  Francis Visoiu Mistrih authored Dec 13, 2017
  b41dbbe3
- [CodeGen] Print target index operands as target-index(target-specific) + 8 in... · b3a0d513
  Francis Visoiu Mistrih authored Dec 13, 2017
  b3a0d513
- [CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and debug output · 26ae8a65
  Francis Visoiu Mistrih authored Dec 13, 2017
  26ae8a65
- [Sema] Ignore decls in namespaces when global decls are not wanted. · fead6ae6
  Eric Liu authored Dec 13, 2017
  fead6ae6
- [mips] Provide additional DSP bitconvert patterns · 0a075d68
  Stefan Maksimovic authored Dec 13, 2017
  0a075d68
- [Testing/Support] Make the HasValue matcher composable · 56c2d999
  Pavel Labath authored Dec 13, 2017
  56c2d999
- [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention · 19c9314a
  Alex Bradbury authored Dec 13, 2017
  19c9314a
- [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted position · 581d6b08
  Alex Bradbury authored Dec 13, 2017
  581d6b08